Take special precaution when collecting data for the first time or when beginning to collect data again after a pause. As explained in the Collecting Data for the First Time or After a Pause in Data CollectionCollecting Data for the First Time or After a Pause in Data CollectionADC Output Buffer and FIFO BufferCollecting Data for the First Time or After a Pause in Data CollectionADC Output Buffer and FIFO Buffer section, the device contains a first-in-first-out (FIFO) buffer in addition to the ADC output buffer. When the host is reading each consecutive sample from the device, both buffers are updated each time new data are generated, so the DRDY flag for each channel in the STATUS register is cleared with each read. However, if data are not read for a period of time, previous samples can be lost as explained in the Collecting Data for the First Time or After a Pause in Data CollectionCollecting Data for the First Time or After a Pause in Data CollectionADC Output Buffer and FIFO BufferCollecting Data for the First Time or After a Pause in Data CollectionADC Output Buffer and FIFO Buffer section. Either strobe the SYNC/RESET pin to resynchronize conversions and clear the buffers, or quickly read two data packets when data are read for the first time or after a gap in reading data. This process ensures predictable DRDY pin behavior. See the SynchronizationSynchronizationSynchronizationSynchronization section for information about the synchronization feature. These methods do not need to be employed if data is read for each output data period from when the ADC is enabled.

Figure 8-26 shows an example of how to collect data after a period of the ADC running, but where no data are being retrieved. In this instance, the SYNC/RESET pin clears the internal buffers and realigns the AMC131M01 output data with the host.

Figure 8-26 Collecting Data After a Pause Using the SYNC/RESET Pin

Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by reading two samples in quick succession. Figure 8-27 shows this method. This example shows that when the DRDY_FMT bit in the MODE register is set to 0b, DRDY is a level output. There is a very narrow pulse on DRDY immediately after the first set of data are shifted out of the device. This pulse can be too narrow for some microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the second data set after the first data set. The host operates synchronous to the device after the second word is read from the device.

Figure 8-27 Collecting Data After a Pause by Reading Data Twice