The AMC131M01 does not generate conversion data automatically after power-up
because the integrated DC/DC converter is disabled initially. For
the ADC to operate, the DC/DC converter must be enabled after
power-up, and a stable supply voltage at the HLDO_OUT pin must be
established that serves as the power supply for the circuitry on the
secondary (high) side.
A recommended procedure
for powering up the AMC131M01 is described in this
section. Figure 8-16 depicts a timing diagram for the device behavior when this
recommended sequence is used. Figure 8-14 provides a flow diagram that displays the recommended sequence in
a graphical form.
Follow these steps to
ensure a correct start-up behavior at power-up:
- Power up the DVDD supply.
- The transition of
DRDY from low to high
indicates a valid supply voltage on the primary side
is established, and also indicates the SPI interface
is ready for communication.
- Configure
the clock divider by setting the CLK_DIV[1:0] bits
in the CLOCK register as needed.
- Configure
the modulator clock frequency by setting the
DCDC_FREQ[3:0] bits in the DCDC_CTRL register; see
the Clocking and Power ModesClocking and Power ModesClocking and Power ModesClocking and Power Modes section for details.
- Enable
the DC/DC converter by setting the DCDC_EN bit in
the DCDC_CTRL register to 1b.
- Configure
all other registers of the AMC131M01
before the external clock is applied to the CLKIN
pin.
- Provide
the main clock at the CLKIN input to start operation
of the integrated DC/DC converter, and to make sure
that the secondary power supply at the HLDO_OUT pin
is generated.
- The
transition of the SEC_FAIL bit in the STATUS
register from high to low indicates that the
secondary power supply at the HLDO_OUT pin is
established and the ADC conversion data output is
valid. Confirm device operation by reading the
SEC_FAIL bit, and verify that this bit is set to 0b,
before reading any conversion data from the ADC.
There are two options for reading the SEC_FAIL bit
in the STATUS register: sending a NULL command
results in a response including the STATUS word, or
sending a register read command to read the STATUS
register. The SEC_FAIL bit is a latched bit;
therefore, at least two read commands are required
to confirm that this bit transitioned from high to
low; the first read command clears the logic high
value that is latched during device power-up. Use
the second read command to verify that the SEC_FAIL
bit is set to 0b, indicating that the secondary
supply is valid. If the SEC_FAIL bit still reads 1b
as a result of the second read command, continue
reading the SEC_FAIL bit until this bit reads 0b
before reading any conversion data from the
ADC.
Regarding the conversion data after power-up, pay attention to the
following:
- The
high-to-low transition of DRDY
indicates that new conversion data are available. As
given in Figure 8-16, ADC data are only valid if the SEC_FAIL reads 0b
during the conversion period. The first two
conversion results shown in Figure 8-16, represent invalid data.
- When the
ADC generates valid data, the digital filter must
settle, as described in the SINC3 and SINC3 + SINC1 Filter section. Two subsequent conversion results
illustrated in Figure 8-16 are unsettled (assuming OSR equals 1024), and the
last conversion result shown provides valid and
settled data.
- For best
control of the conversion timing, especially in a
system where multiple devices of the AMC131M01 are used, trigger a
synchronization using the
SYNC/RESET
pin before the host collects conversion data from
the ADC. See the SynchronizationSynchronizationSynchronizationSynchronization section for more details regarding how to
synchronize the device.
In Figure 8-16, tPOR_SEC is the time from enabling the DC/DC
converter to the first falling edge of the SEC_FAIL bit, which
indicates that the secondary power supply at the HLDO_OUT pin is
stable. tPOR_DVDD is the time from DVDD supply at 90% to
DRDY first rising edge.