The ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear-phase, finite impulse response (FIR), low-pass, sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter are decimated and downsampled to reduce the rate at which data come out of the modulator (f_MOD) to the output data rate (f_DATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. By setting the OSR[2:0] bits, the OSR can be configured in values ranging from 128 to 16384 in binary steps. In addition, the OSR can be configured to a value of 64 by setting the TURBO bit in the CLOCK register (turbo mode). Therefore in total, there are nine OSR settings in the AMC131M03-Q1, allowing nine different data rate settings for any given main clock frequency. Table 8-4 lists the OSR settings and the corresponding output data rates for the nominal CLKIN frequencies mentioned, assuming the programmable clock divider is set to N_DIV = 2.

The OSR determines the amount of averaging of the modulator output in the digital filter and, therefore, also the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth results in lower noise, whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings.

The device must be in standby mode when changing the OSR. Setting the OSR[2:0] bits to a new value while the ADC is generating conversion data can result in unexpected behavior of the ADC output.