JAJSP50A May 2023 – September 2023 AMC131M03-Q1
PRODUCTION DATA
The DRDY pin is an active-low output that indicates when new conversion data are ready in conversion mode. Connect the DRDY pin to an input on the host to trigger periodic data retrieval in conversion mode. The period between each DRDY falling edge is the data rate period.
The timing of DRDY with respect to the sampling of a given channel on the AMC131M03-Q1 depends on the phase calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting the DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts DRDY each time any channel data are ready. Finally, setting the bits to either 10b or 11b configures the device to assert DRDY when the channel with the most negative phase calibration setting, or the most leading, has new conversion data. Changing the DRDY_SEL[1:0] bits has no effect on DRDY behavior in global-chop mode because phase calibration is automatically disabled in global-chop mode.
The timing of the first DRDY assertion after channels are enabled or after a synchronization pulse is provided depends on the phase calibration setting. If the channel that causes DRDY to assert has a phase calibration setting less than zero, the first DRDY assertion can be less than one sample period from the channel being enabled or the occurrence of the synchronization pulse. However, DRDY asserts in the next sample period if the phase setting puts the output timing too close to the beginning of the sample period.
Table 8-9 lists the phase calibration setting boundary at which DRDY either first asserts within a sample period, or in the next sample period. If the setting for the channel configured to control DRDY assertion is greater than the value listed in Table 8-9 for each OSR, DRDY asserts for the first time within a sample period of the channel being enabled or the synchronization pulse. If the phase setting value is equal to or more negative than the value in Table 8-9, DRDY asserts in the following sample period. See the Synchronization section for more information about synchronization.
| OSR | PHASE SETTING BOUNDARY | PHASEn[9:0] BIT SETTING BOUNDARY |
|---|---|---|
| 128 | –19 | 3EDh |
| 256 | –83 | 3ADh |
| 512 | –211 | 32Dh |
| 1024 | –467 | 22Dh |
| >1024 | None | N/A |
The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 10-kΩ pullup resistor to pull the pin high when DRDY is not asserted.
The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new data are indicated by DRDY changing from high to low and remaining low until either all conversion data are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If the host does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a conversion result and does not provide another DRDY pulse until the second following instance when data are ready because of how the pulse is generated. See the Collecting Data for the First Time or After a Pause in Data Collection section for more information about the behavior of DRDY when data are not consistently read.