JAJSP50A May   2023  – September 2023 AMC131M03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 Temperature Sensor
        1. 8.3.15.1 Internal Temperature Sensor
        2. 8.3.15.2 External Temperature Sensor
        3. 8.3.15.3 Clock Selection for Temperature Sensor Operation
      16. 8.3.16 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M03-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3 Power Supply Recommendations

The AMC131M03-Q1 is powered from the low-side power supply (DVDD) with a nominal value of 3.3 V (or 5 V) ± 10%. Place a low-ESR decoupling capacitor of 1 nF (C15 in Figure 9-6) as close as possible to the DVDD pin, followed by a 1-µF capacitor (C16) to filter this power-supply path.

The low-side power supply (DVDD) is the only external supply required to operate the AMC131M03-Q1. All internal voltage supplies and secondary (high-side) supplies are generated by the integrated DC/DC converter and the high-side LDO, such as the supply voltage at the output pins, DCDC_OUT and HLDO_OUT.

The primary-side of the DC/DC converter is decoupled with a low-ESR, 100-nF capacitor (C17) positioned close to the device between the DCDC_CAP and DGND pins. Use a 1-µF capacitor (C6) to decouple the high-side in addition to a low-ESR, 1-nF capacitor (C1) placed as close as possible to the device and connected between the DCDC_OUT and DCDC_HGND pins.

For improved EMI performance, place a ferrite bead between the DCDC_OUT and HLDO_IN pins (F1) and the DCDC_HGND and HGND pins (F2), respectively.

For the high-side LDO, use low-ESR capacitors of 1 nF (C11) placed as close as possible to the AMC131M03-Q1, followed by a 100-nF decoupling capacitor (C13) between the HLDO_OUT and HGND pins.

The ground reference for the high-side (HGND) is derived from the terminal of the shunt resistor that is connected to the negative input (AIN0N) of the device. For best DC accuracy, use a separate trace to make this connection instead of shorting HGND to AIN0N directly at the device input.

GUID-20230503-SS0I-WXHD-0VLP-VPXWPWJJTCNP-low.svg Figure 9-6 Power Supply Decoupling the AMC131M03-Q1

Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they experience in the application. MLCC capacitors typically exhibit only a fraction of the nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves that greatly simplify component selection.

Table 9-3 lists components suitable for use with the AMC131M03-Q1. This list is not exhaustive. Other components can exist that are equally suitable (or better), however these listed components have been validated during the development of the AMC131M03-Q1.

Table 9-3 Recommended External Components
COMP DESCRIPTION PART NUMBER MANUFACTURER SIZE (EIA, L x W)
DVDD
C15 1 nF ± 10%, X7R, 50 V 12065C102KAT2A AVX 1206, 3.2 mm x 1.6 mm
C16 1 µF ± 10%, X7R, 25 V 12063C105KAT2A AVX 1206, 3.2 mm x 1.6 mm
DC/DC CONVERTER
C17 100 nF ± 10%, X7R, 50 V C0603C104K5RACAUTO Kemet 0603, 1.6 mm x 0.8 mm
C1 1 nF ± 10%, X7R, 50 V C0603C102K5RACTU Kemet 0603, 1.6 mm x 0.8 mm
C6 1 µF ± 10%, X7R, 25 V CGA3E1X7R1E105K080AC TDK 0603, 1.6 mm x 0.8 mm
F1, F2 Ferrite bead 74269244182 Wurth Elektronik 0402, 1.0 mm x 0.5 mm
HLDO
C24 100 nF ± 10%, X7R, 50 V C0603C104K5RACAUTO Kemet 0603, 1.6 mm x 0.8 mm
C10 1 nF ± 10%, X7R, 50 V 12065C102KAT2A AVX 1206, 3.2 mm x 1.6 mm
C13 100 nF ± 5%, NP0, 50 V C3216NP01H104J160AA TDK 1206, 3.2 mm x 1.6 mm
C11 1 nF ± 10%, X7R, 50 V 12065C102KAT2A AVX 1206, 3.2 mm x 1.6 mm