JAJSOS3B September   2023  – September 2023 AMC131M03

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 Temperature Sensor
        1. 8.3.15.1 Internal Temperature Sensor
        2. 8.3.15.2 External Temperature Sensor
        3. 8.3.15.3 Clock Selection for Temperature Sensor Operation
      16. 8.3.16 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M03 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement
        2. 9.2.2.2 Current Shunt Measurement
        3. 9.2.2.3 Temperature Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 AMC131M03 Registers

Table 8-14 lists the memory-mapped registers for the AMC131M03 registers. All register offset addresses not listed in Table 8-14 should be considered as reserved locations and the register contents should not be modified.

Table 8-14 Register Map
Address Acronym Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h ID Xb RESERVED CHANCNT[3:0]
RESERVED
01h STATUS 0540h LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
FUSE_FAIL SEC_FAIL RESERVED DRDY2 DRDY1 DRDY0
02h MODE 0510h RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT
03h CLOCK 070Eh RESERVED CH2_EN CH1_EN CH0_EN
CLK_DIV[1:0] TURBO OSR[2:0] PWR[1:0]
04h GAIN 0000h RESERVED PGAGAIN2[2:0]
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
06h CFG 0600h RESERVED GPO_EN GPO_DAT GC_DLY[3:0] GC_EN
RESERVED
09h CH0_CFG 0000h PHASE0[9:0]
PHASE0[9:0] RESERVED MUX0[1:0]
0Ah CH0_OCAL_MSB 0000h OCAL0_MSB[15:0]
OCAL0_MSB[15:0]
0Bh CH0_OCAL_LSB 0000h OCAL0_LSB[7:0]
RESERVED
0Ch CH0_GCAL_MSB 8000h GCAL0_MSB[15:0]
GCAL0_MSB[15:0]
0Dh CH0_GCAL_LSB 0000h GCAL0_LSB[7:0]
RESERVED
0Eh CH1_CFG 0000h PHASE1[9:0]
PHASE1[9:0] RESERVED MUX1[1:0]
0Fh CH1_OCAL_MSB 0000h OCAL1_MSB[15:0]
OCAL1_MSB[15:0]
10h CH1_OCAL_LSB 0000h OCAL1_LSB[7:0]
RESERVED
11h CH1_GCAL_MSB 8000h GCAL1_MSB[15:0]
GCAL1_MSB[15:0]
12h CH1_GCAL_LSB 0000h GCAL1_LSB[7:0]
RESERVED
13h CH2_CFG 0000h PHASE2[9:0]
PHASE2[9:0] TS_SEL TS_EN RESERVED TS_CHOP MUX2[1:0]
14h CH2_OCAL_MSB 0000h OCAL2_MSB[15:0]
OCAL2_MSB[15:0]
15h CH2_OCAL_LSB 0000h OCAL2_LSB[7:0]
RESERVED
16h CH2_GCAL_MSB 8000h GCAL2_MSB[15:0]
GCAL2_MSB[15:0]
17h CH2_GCAL_LSB 0000h GCAL2_LSB[7:0]
RESERVED
31h DCDC_CTRL 0000h RESERVED DCDC_FREQ[3:0]
RESERVED DCDC_EN
3Eh REGMAP_CRC 0000h REG_CRC[15:0]
REG_CRC[15:0]

Complex bit access types are encoded to fit into small table cells. Table 8-15 shows the codes that are used for access types in this section.

Table 8-15 AMC131M03 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

8.6.1 ID Register (Address = 00h) [Reset = 23XXh]

Return to the Summary Table.

Figure 8-33 ID Register
15 14 13 12 11 10 9 8
RESERVED CHANCNT[3:0]
R-0010b R-0011b
7 6 5 4 3 2 1 0
RESERVED
R-X
Table 8-16 ID Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R 0010b Reserved
Always reads 0010b
11:8 CHANCNT[3:0] R 0011b Channel count
Always reads 0011b
7:0 RESERVED R X Reserved
Values are subject to change without notice.

8.6.2 STATUS Register (Address = 01h) [Reset = 0540h]

Return to the Summary Table.

Figure 8-34 STATUS Register
15 14 13 12 11 10 9 8
LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
R-0b R-0b R-0b R-0b R-0b R-1b R-01b
7 6 5 4 3 2 1 0
FUSE_FAIL SEC_FAIL RESERVED DRDY2 DRDY1 DRDY0
R-0b R-1b R-000b R-0b R-0b R-0b
Table 8-17 STATUS Register Field Descriptions
Bit Field Type Reset Description
15 LOCK R 0b SPI interface lock indicator
Indicates the SPI interface is locked by the lock command. The bit is reset to 0b by the unlock command.
0b = Unlocked
1b = Locked
14 F_RESYNC R 0b ADC resynchronization indicator
This bit is set each time the ADC resynchronizes. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No resynchronization occurred
1b = Resynchronization occurred
13 REG_MAP R 0b Register map CRC fault indicator
Indicates a register map CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No register map CRC fault occurred
1b = Register map CRC fault occurred
12 CRC_ERR R 0b SPI input CRC error indicator
Indicates a SPI input CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No CRC error
1b = Input CRC error occurred
11 CRC_TYPE R 0b CRC type indicator
Indicates the CRC type. This bit is cleared by a device reset.
0b = 16-bit CCITT
1b = 16-bit ANSI
10 RESET R 1b Reset status indicator
The device reset indicator is triggered by the RESET pin, power-on-reset or the RESET command. This bit is cleared by writing 0b to the RESET bit in the MODE register.
0b = Not reset
1b = Reset occurred
9:8 WLENGTH[1:0] R 01b Data word length indicator
Indicates the data word frame length. This bit is cleared by a device reset.
00b = 16 bit
01b = 24 bits
10b = 32 bits; zero padding
11b = 32 bits; MSB sign extension
7 FUSE_FAIL R 0b Fuse parity fault indicator
Indicates a fault of the internal memory. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. If the physical fault persists, the indicator is set again automatically.
0b = Fuse parity OK
1b = Fuse parity not OK
6 SEC_FAIL R 1b High-side supply fault indicator
Indicates a fault of the high-side output of the DC/DC converter, or a communication error during the data transmission across the isolation barrier. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = High-side supply OK
1b = High-side supply not OK
5:3 RESERVED R 000b Reserved
Always reads 000b
2 DRDY2 R 0b Channel 2 ADC data available indicator

0b = No new data available
1b = New data are available
1 DRDY1 R 0b Channel 1 ADC data available indicator

0b = No new data available
1b = New data are available
0 DRDY0 R 0b Channel 0 ADC data available indicator

0b = No new data available
1b = New data are available

8.6.3 MODE Register (Address = 02h) [Reset = 0510h]

Return to the Summary Table.

Figure 8-35 MODE Register
15 14 13 12 11 10 9 8
RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b
7 6 5 4 3 2 1 0
RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT
R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b
Table 8-18 MODE Register Field Descriptions
Bit Field Type Reset Description
15:14 RESERVED R/W 00b Reserved
Always write 00b
13 REG_CRC_EN R/W 0b Register map CRC enable

0b = Disabled
1b = Enabled
12 RX_CRC_EN R/W 0b SPI input CRC enable

0b = Disabled
1b = Enabled
11 CRC_TYPE R/W 0b SPI input and output, register map CRC type

0b = 16-bit CCITT
1b = 16-bit ANSI
10 RESET R/W 1b Reset
Write 0b to clear the RESET bit in the STATUS register
0b = No reset
1b = Reset occurred
9:8 WLENGTH[1:0] R/W 01b Data word length selection

00b = 16 bits
01b = 24 bits
10b = 32 bits; LSB zero padding
11b = 32 bits; MSB sign extension
7:5 RESERVED R/W 000b Reserved
Always write 000b
4 TIMEOUT R/W 1b SPI timeout enable

0b = Disabled
1b = Enabled
3:2 DRDY_SEL[1:0] R/W 00b DRDY pin signal source selection

00b = Most lagging enabled channel
01b = Logic OR of all the enabled channels
10b = Most leading enabled channel
11b = Most leading enabled channel
1 DRDY_HiZ R/W 0b DRDY pin state when conversion data are not available

0b = Logic high
1b = High impedance
0 DRDY_FMT R/W 0b DRDY signal format when conversion data are available

0b = Logic low
1b = Low pulse with a fixed duration

8.6.4 CLOCK Register (Address = 03h) [Reset = 070Eh]

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Figure 8-36 CLOCK Register
15 14 13 12 11 10 9 8
RESERVED CH2_EN CH1_EN CH0_EN
R/W-00000b R/W-1b R/W-1b R/W-1b
7 6 5 4 3 2 1 0
CLK_DIV[1:0] TURBO OSR[2:0] PWR[1:0]
R/W-00b R/W-0b R/W-011b R/W-10b
Table 8-19 CLOCK Register Field Descriptions
Bit Field Type Reset Description
15:11 RESERVED R/W 00000b Reserved
Always write 00000b
10 CH2_EN R/W 1b Channel 2 ADC enable

0b = Disabled
1b = Enabled
9 CH1_EN R/W 1b Channel 1 ADC enable

0b = Disabled
1b = Enabled
8 CH0_EN R/W 1b Channel 0 ADC enable

0b = Disabled
1b = Enabled
7:6 CLK_DIV[1:0] R/W 00b Clock divider ratio selection

00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 12
5 TURBO R/W 0b Turbo mode (OSR = 64)
Selects oversampling ratio 64 by setting this bit to 1b. The OSR[2:0] bits are ignored if this bit is set to 1b.
0b = Disabled
1b = Enabled
4:2 OSR[2:0] R/W 011b Modulator oversampling ratio selection

000b = 128
001b = 256
010b = 512
011b = 1024
100b = 2048
101b = 4096
110b = 8192
111b = 16384
1:0 PWR[1:0] R/W 10b Power mode selection

00b = Reserved. Do not use.
01b = Low power
10b = High resolution
11b = Reserved. Do not use.

8.6.5 GAIN Register (Address = 04h) [Reset = 0000h]

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Figure 8-37 GAIN Register
15 14 13 12 11 10 9 8
RESERVED PGAGAIN2[2:0]
R/W-00000b R/W-000b
7 6 5 4 3 2 1 0
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
R/W-0b R/W-000b R/W-0b R/W-000b
Table 8-20 GAIN Register Field Descriptions
Bit Field Type Reset Description
15:11 RESERVED R/W 00000b Reserved
Always write 00000b
10:8 PGAGAIN2[2:0] R/W 000b PGA gain selection for channel 2

000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
7 RESERVED R/W 0b Reserved
Always write 0b
6:4 PGAGAIN1[2:0] R/W 000b PGA gain selection for channel 1

000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
3 RESERVED R/W 0b Reserved
Always write 0b
2:0 PGAGAIN0[2:0] R/W 000b PGA gain selection for channel 0

000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128

8.6.6 CFG Register (Address = 06h) [Reset = 0600h]

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Figure 8-38 CFG Register
15 14 13 12 11 10 9 8
RESERVED GPO_EN GPO_DAT GC_DLY[3:0] GC_EN
R/W-0b R/W-0b R/W-0b R/W-0011b R/W-0b
7 6 5 4 3 2 1 0
RESERVED
R/W-00000000b
Table 8-21 CFG Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R/W 0b Reserved
Always write 0b
14 GPO_EN R/W 0b Digital output enable
Enables digital output (GPO) functionality at AIN2P pin.
0b = Digital output disabled
1b = Digital output enabled
13 GPO_DAT R/W 0b Digital output data
Digital output (GPO) data if GPO_EN = 1b.
0b = Zero output
1b = One output
12:9 GC_DLY[3:0] R/W 0011b Global-chop delay selection
Delay in modulator clock periods before measurement begins.
0000b = 2
0001b = 4
0010b = 8
0011b = 16
0100b = 32
0101b = 64
0110b = 128
0111b = 256
1000b = 512
1001b = 1024
1010b = 2048
1011b = 4096
1100b = 8192
1101b = 16384
1110b = 32768
1111b = 65536
8 GC_EN R/W 0b Global-chop enable

0b = Disabled
1b = Enabled
7:0 RESERVED R/W 00000000b Reserved
Always write 00000000b

8.6.7 CH0_CFG Register (Address = 09h) [Reset = 0000h]

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Figure 8-39 CH0_CFG Register
15 14 13 12 11 10 9 8
PHASE0[9:0]
R/W-0000000000b
7 6 5 4 3 2 1 0
PHASE0[9:0] RESERVED MUX0[1:0]
R/W-0000000000b R-0000b R/W-00b
Table 8-22 CH0_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 PHASE0[9:0] R/W 0000000000b Channel 0 phase delay selection
Phase delay in modulator clock cycles provided in twos complement format.
5:2 RESERVED R 0000b Reserved
Always reads 0000b
1:0 MUX0[1:0] R/W 00b Channel 0 input selection
Input multiplexer for channel 0
00b = AIN0P and AIN0N
01b = AIN0 disconnected (ADC inputs shorted)
10b = DC diagnostic signal
11b = AC diagnostic signal

8.6.8 CH0_OCAL_MSB Register (Address = 0Ah) [Reset = 0000h]

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Figure 8-40 CH0_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL0_MSB[15:0]
R/W-0000000000000000b
7 6 5 4 3 2 1 0
OCAL0_MSB[15:0]
R/W-0000000000000000b
Table 8-23 CH0_OCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 OCAL0_MSB[15:0] R/W 0000000000000000b Channel 0 offset calibration register bits [23:8]
Value provided in twos complement format.

8.6.9 CH0_OCAL_LSB Register (Address = 0Bh) [Reset = 0000h]

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Figure 8-41 CH0_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL0_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-24 CH0_OCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 OCAL0_LSB[7:0] R/W 00000000b Channel 0 offset calibration register bits [7:0]
Value provided in twos complement format.
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.10 CH0_GCAL_MSB Register (Address = 0Ch) [Reset = 8000h]

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Figure 8-42 CH0_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL0_MSB[15:0]
R/W-1000000000000000b
7 6 5 4 3 2 1 0
GCAL0_MSB[15:0]
R/W-1000000000000000b
Table 8-25 CH0_GCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 GCAL0_MSB[15:0] R/W 1000000000000000b Channel 0 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224

8.6.11 CH0_GCAL_LSB Register (Address = 0Dh) [Reset = 0000h]

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Figure 8-43 CH0_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL0_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-26 CH0_GCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 GCAL0_LSB[7:0] R/W 00000000b Channel 0 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.12 CH1_CFG Register (Address = 0Eh) [Reset = 0000h]

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Figure 8-44 CH1_CFG Register
15 14 13 12 11 10 9 8
PHASE1[9:0]
R/W-0000000000b
7 6 5 4 3 2 1 0
PHASE1[9:0] RESERVED MUX1[1:0]
R/W-0000000000b R-0000b R/W-00b
Table 8-27 CH1_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 PHASE1[9:0] R/W 0000000000b Channel 1 phase delay selection
Phase delay in modulator clock cycles provided in twos complement format.
5:2 RESERVED R 0000b Reserved
Always reads 0000b
1:0 MUX1[1:0] R/W 00b Channel 1 input selection
Input multiplexer for channel 1
00b = AIN1P and AIN12N
01b = AIN1 disconnected (ADC inputs shorted)
10b = DC diagnostic signal
11b = AC diagnostic signal

8.6.13 CH1_OCAL_MSB Register (Address = 0Fh) [Reset = 0000h]

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Figure 8-45 CH1_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL1_MSB[15:0]
R/W-0000000000000000b
7 6 5 4 3 2 1 0
OCAL1_MSB[15:0]
R/W-0000000000000000b
Table 8-28 CH1_OCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 OCAL1_MSB[15:0] R/W 0000000000000000b Channel 1 offset calibration register bits [23:8]
Value provided in twos complement format.

8.6.14 CH1_OCAL_LSB Register (Address = 10h) [Reset = 0000h]

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Figure 8-46 CH1_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL1_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-29 CH1_OCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 OCAL1_LSB[7:0] R/W 00000000b Channel 1 offset calibration register bits [7:0]
Value provided in twos complement format.
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.15 CH1_GCAL_MSB Register (Address = 11h) [Reset = 8000h]

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Figure 8-47 CH1_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL1_MSB[15:0]
R/W-1000000000000000b
7 6 5 4 3 2 1 0
GCAL1_MSB[15:0]
R/W-1000000000000000b
Table 8-30 CH1_GCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 GCAL1_MSB[15:0] R/W 1000000000000000b Channel 1 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224

8.6.16 CH1_GCAL_LSB Register (Address = 12h) [Reset = 0000h]

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Figure 8-48 CH1_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL1_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-31 CH1_GCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 GCAL1_LSB[7:0] R/W 00000000b Channel 1 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.17 CH2_CFG Register (Address = 13h) [Reset = 0000h]

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Figure 8-49 CH2_CFG Register
15 14 13 12 11 10 9 8
PHASE2[9:0]
R/W-0000000000b
7 6 5 4 3 2 1 0
PHASE2[9:0] TS_SEL TS_EN RESERVED TS_CHOP MUX2[1:0]
R/W-0000000000b R/W-0b R/W-0b R-0b R/W-0b R/W-00b
Table 8-32 CH2_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 PHASE2[9:0] R/W 0000000000b Channel 2 phase delay selection
Phase delay in modulator clock cycles provided in twos complement format.
5 TS_SEL R/W 0b Temperature sensor input selection
Selects between internal and external temperature sensor.
0b = Internal sensor
1b = External sensor
4 TS_EN R/W 0b Temperature sensor measurement mode enable

0b = Temperature sensor disabled
1b = Temperature sensor enabled
3 RESERVED R 0b Reserved
Always reads 0000b
2 TS_CHOP R/W 0b Temperature sensor input polarity selection
Inverts the temperature sensor inputs.
0b = Temperature sensor inputs are not inverted
1b = Temperature sensor inputs are inverted
1:0 MUX2[1:0] R/W 00b Channel 2 input selection
Input multiplexer for channel 2
00b = AIN2P and AIN12N
01b = AIN2 disconnected (ADC inputs shorted)
10b = DC diagnostic signal
11b = AC diagnostic signal

8.6.18 CH2_OCAL_MSB Register (Address = 14h) [Reset = 0000h]

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Figure 8-50 CH2_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL2_MSB[15:0]
R/W-0000000000000000b
7 6 5 4 3 2 1 0
OCAL2_MSB[15:0]
R/W-0000000000000000b
Table 8-33 CH2_OCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 OCAL2_MSB[15:0] R/W 0000000000000000b Channel 2 offset calibration register bits [23:8]
Value provided in twos complement format.

8.6.19 CH2_OCAL_LSB Register (Address = 15h) [Reset = 0000h]

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Figure 8-51 CH2_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL2_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-34 CH2_OCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 OCAL2_LSB[7:0] R/W 00000000b Channel 2 offset calibration register bits [7:0]
Value provided in twos complement format.
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.20 CH2_GCAL_MSB Register (Address = 16h) [Reset = 8000h]

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Figure 8-52 CH2_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL2_MSB[15:0]
R/W-1000000000000000b
7 6 5 4 3 2 1 0
GCAL2_MSB[15:0]
R/W-1000000000000000b
Table 8-35 CH2_GCAL_MSB Register Field Descriptions
Bit Field Type Reset Description
15:0 GCAL2_MSB[15:0] R/W 1000000000000000b Channel 2 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224

8.6.21 CH2_GCAL_LSB Register (Address = 17h) [Reset = 0000h]

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Figure 8-53 CH2_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL2_LSB[7:0]
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED
R-00000000b
Table 8-36 CH2_GCAL_LSB Register Field Descriptions
Bit Field Type Reset Description
15:8 GCAL2_LSB[7:0] R/W 00000000b Channel 2 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

8.6.22 DCDC_CTRL Register (Address = 31h) [Reset = 0000h]

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Figure 8-54 DCDC_CTRL Register
15 14 13 12 11 10 9 8
RESERVED DCDC_FREQ[3:0]
R/W-0000b R/W-0000b
7 6 5 4 3 2 1 0
RESERVED DCDC_EN
R/W-0000000b R/W-0b
Table 8-37 DCDC_CTRL Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R/W 0000b Reserved
Always write 0000b
11:8 DCDC_FREQ[3:0] R/W 0000b DC/DC frequency range selection
Selects the range of the modulator clock frequency, based on the frequency at the CLKIN pin and clock divider ratio.
0000b = 3.76 MHz to 4.10 MHz
0001b = 3.52 MHz to 3.84 MHz
0010b = 3.30 MHz to 3.59 MHz
0011b = 3.09 MHz to 3.36 MHz
0100b = 2.89 MHz to 3.15 MHz
0101b = 2.71 MHz to 2.95 MHz
0110b = 2.53 MHz to 2.76 MHz
0111b = 2.37 MHz to 2.59 MHz
1000b = 2.22 MHz to 2.42 MHz
1001b = 2.08 MHz to 2.27 MHz
1010b = 1.95 MHz to 2.12 MHz
1011b = 1.82 MHz to 1.99 MHz
1100b = 1.71 MHz to 1.86 MHz
1101b = 1.60 MHz to 1.74 MHz
1110b = 1.50 MHz to 1.63 MHz
1111b = 1.40 MHz to 1.53 MHz
7:1 RESERVED R/W 0000000b Reserved
Always write 0000000b
0 DCDC_EN R/W 0b DC/DC enable
Enables the integrated DC/DC converter.
0b = Disabled
1b = Enabled

8.6.23 REGMAP_CRC Register (Address = 3Eh) [Reset = 0000h]

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Figure 8-55 REGMAP_CRC Register
15 14 13 12 11 10 9 8
REG_CRC[15:0]
R-0000000000000000b
7 6 5 4 3 2 1 0
REG_CRC[15:0]
R-0000000000000000b
Table 8-38 REGMAP_CRC Register Field Descriptions
Bit Field Type Reset Description
15:0 REG_CRC[15:0] R 0000000000000000b Register map CRC value