The modulator generates a bitstream that is required to be processed by a digital filter. This process obtains a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, as shown in Equation 2, built with minimal effort and hardware, is a sinc³-type filter:

Equation 2.

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All characterization in this document is done with a 256 OSR sinc³ filter and a 16-bit output word width, unless otherwise noted. The measured effective number of bits (ENOB) as a function of the OSR is illustrated in Figure 7-3 of the Typical Application section.

A delta sigma modulator filter calculator is available for download at www.ti.com. This calculator aids in the filter design and correct OSR and filter-order selection to achieve the desired output resolution and filter response time.

The Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available at www.ti.com, discusses an example code. This example code implements a sinc³ filter in an FPGA.