Figure 6-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC3306M25-Q1. The output V₅ of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage V_IN = (V_INN – V_INP) and results in a voltage V₁. V₁ feeds the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in an output voltage V₃. V₃ is summed with the input signal V_IN and the output of the first integrator V₂. Depending on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V₅. This change causes the integrators to progress in the opposite direction and forces the value of the integrator output to track the average input value.

Figure 6-2 Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies, as illustrated in Figure 6-1. Therefore, use a low-pass digital filter, such as a SINC filter, at the output of the device to increase signal to noise ratio. This filter also converts the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000™ and Sitara™ microcontroller families offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC3306M25-Q1. Alternatively, use a field-programmable gate array (FPGA) or complex programmable logic device (CPLD) to implement the filter.