JAJSS43 August   2024 AMC3306M25-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications 
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Insulation Characteristics Curves
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 6.3.4.2 Output Behavior in Case of a High-Side Supply Failure
      5. 6.3.5 Isolated DC/DC Converter
      6. 6.3.6 Diagnostic Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Digital Filter Usage
    2. 7.2 Typical Application
      1. 7.2.1 Onboard Charger (OBC) Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Shunt Resistor Sizing
          2. 7.2.1.2.2 Input Filter Design
          3. 7.2.1.2.3 Bitstream Filtering
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Best Design Practices
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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発注情報

5.9 Electrical Characteristics

all minimum and maximum specifications are at TA = –40°C to +125°C, VDD = 3.0V to 5.5V, INP = –250mV to +250mV, INN = 0V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20MHz, VDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Single-ended input resistance INN = HGND 19 kΩ
RIND Differential input resistance 22 kΩ
IIB Input bias current INP = INN = HGND;
IIB = (IIBP + IIBN) / 2		 –41 –30 –24 μA
IIO Input offset current(1) IIO = IIBP – IIBN; INP = INN = HGND ±10 nA
CIN Single-ended input capacitance INN = HGND, fIN = 310kHz 2 pF
CIND Differential input capacitance fIN = 310kHz 1 pF
ACCURACY
EO Offset error(1) INN = INP = HGND, TA = 25°C –50 ±10 50 µV
TCEO Offset error thermal drift(4) INN = INP = HGND –1 1 µV/°C
EG Gain error TA = 25°C –0.2% ±0.005% 0.2% %
TCEG Gain error drift(5) –35 35 ppm/°C
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity Resolution: 16 bits –4 ±1 4 LSB
SNR Signal-to-noise ratio fIN = 1kHz 81 83 dB
SINAD Signal-to-noise + distortion fIN = 1kHz 79 82.5 dB
THD Total harmonic distortion(3) 5MHz ≤ fCLKIN ≤ 21MHz, fIN = 1kHz –96 –88 dB
SFDR Spurious-free dynamic range fIN = 1kHz 88 97 dB
CMRR Common-mode rejection ratio fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max –95 dB
fIN = 10kHz, VCM min ≤ VIN ≤ VCM max, VINP = VINN = 500mVPP –84
PSRR Power-supply rejection ratio VDD from 3.0V to 5.5V, at DC –120 dB
INP = INN = HGND, VDD from 3.0V to 5.5V, 10 kHz, 100mV ripple –120
DIGITAL I/O
IIN Input leakage current GND ≤ VIN ≤ VDD 0 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × VDD VDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × VDD V
CLOAD Output load capacitance 15 30 pF
VOH High-level output voltage IOH = –20µA VDD – 0.1 V
IOH = –4mA VDD – 0.4
VOL Low-level output voltage IOL = 20µA 0.1 V
IOL = 4mA 0.4
CMTI Common-mode transient immunity 75 135 kV/μs
POWER SUPPLY
IDD Low-side supply current No external load on HLDO 26 40 mA
1mA external load on HLDO 28 42
VDDUV VDD analog undervoltage detection threshold VDD rising 2.9 V
VDD falling 2.8
VDDPOR VDD digital reset threshold VDD rising 2.5 V
VDD falling 2.4
VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND 3.1 3.5 4.65 V
VDCDCUV DC/DC output undervoltage detection threshold voltage VDCDC_OUT falling 2.1 2.25 V
VHLDO_OUT High-side LDO output voltage HLDO_OUT to HGND, up to 1mA external load(2) 3 3.2 3.4 V
VHLDOUV High-side LDO output undervoltage detection threshold voltage VHLDO_OUT falling 2.4 2.6 V
IH High-side supply current for auxiliary circuitry Load connected from HLDO_OUT to HGND; non-switching;
–40℃ ≤ TA ≤ 85℃(2)		 1 mA
tSTART Device startup time VDD step to 3.0V to bitstream valid 0.9 1.4 ms
(1) The typical value includes one sigma statistical variation at nominal operating conditions.
(2) High-side LDO supports full external load (IH) only up to TA = 85℃. See the Isolated DC/DC Converter section for more details.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX – EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the temperature range (–40 to 125℃).
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).