JAJSPF2A june   2023  – august 2023 AMC3311

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
      4. 7.3.4 Isolated DC/DC Converter
      5. 7.3.5 Diagnostic Output and Fail-Safe Behavior
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, and IN = –0.1 V to 2 V; typical specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Input resistance TA = 25℃ 1 GΩ
IIB Input bias current IN = HGND, TA = 25℃ –15 3.5 15 nA
TCIIB Input bias current drift(1) ±12 pA/°C
CIN Input capacitance fIN = 275 kHz 7 pF
ANALOG OUTPUT
Nominal gain 1 V/V
VCMout Common-mode output voltage 1.39 1.44 1.49 V
VCLIPout Clipping differential output voltage VOUT = (VOUTP – VOUTN);
VIN > VClipping		 2.49 V
VFAILSAFE Failsafe differential output voltage VOUT = (VOUTP – VOUTN);
VDCDC_OUT ≤ VDCDCUV, or
VHLDO_OUT ≤ VHLDOUV		 –2.6 –2.5 V
BW Output bandwidth 220 275 kHz
ROUT Output resistance On OUTP or OUTN 0.2 Ω
Output short-circuit current On OUTP or OUTN, sourcing or sinking, IN = HGND, outputs shorted to either GND or VDD 14 mA
CMTI Common-mode transient immunity 85 135 kV/µs
ACCURACY
VOS Input offset voltage(1)(2) TA = 25°C, IN = HGND –1 ±0.1 1 mV
TCVOS Input offset thermal drift(1)(2)(4) –10 ±3 10 µV/°C
EG Gain error TA = 25°C –0.2% ±0.05% 0.2%
TCEG Gain error drift(1)(5) –40 ±5 40 ppm/°C
Nonlinearity –0.02% ±0.01% 0.02%
Nonlinearity thermal drift 1 ppm/°C
SNR Signal-to-noise ratio VIN = 2 VPP, VIN > 0 V,
fIN = 1 kHz, BW = 10 kHz,
10 kHz filter		 75.5 78.4 dB
VIN = 2 VPP, VIN > 0 V,
fIN = 10 kHz, BW = 100 kHz,
1 MHz filter		 67.5
THD Total harmonic distortion(3) VIN = 2 Vpp, VIN > 0 V, 
fIN = 10 kHz, BW = 100 kHz		 –80.6 dB
Output noise IN = HGND, BW = 100 kHz 250 µVRMS
PSRR Power-supply rejection ratio(2) VDD from 3.0 V to 5.5 V, at DC –85 dB
IN = HGND, VDD from 3.0 V to 5.5 V,
10-kHz, 100-mV ripple		 –70
POWER SUPPLY
IDD Low-side supply current No external load on HLDO 28.5 41 mA
4 mA  external load on HLDO 36.5 49 mA
VDDUV VDD analog undervoltage detection threshold VDD rising 2.9 V
VDD falling 2.8
VDDPOR VDD digital reset threshold VDD rising 2.5 V
VDD falling 2.4
VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND 3.1 3.4 4.65 V
VDCDCUV DC/DC output undervoltage detection threshold voltage DCDC output falling 2.1 2.25 V
VHLDO_OUT High-side LDO output voltage HLDO to HGND, no external load 3 3.2 3.4 V
HLDO to HGND, 4 mA external load, VDD > 3.6 V 3 3.2 3.4
VHLDOUV High-side LDO output undervoltage detection threshold voltage HLDO output falling 2.4 2.6 V
IH High-side supply current for auxiliary circuitry 3 V ≤ VDD < 3.6 V, load connected from HLDO_OUT to HGND, non-switching 1 mA
3.6 V ≤ VDD ≤ 5.5 V, load connected from HLDO_OUT to HGND, non-switching 4.0
tAS Analog settling time VDD step to 3.0 V, to OUTP and OUTN valid, 0.1% settling 0.6 1.1 ms
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditons.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured within the temperature range (–40 to 125℃).
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).