JAJSPB8A June 2009 – January 2023 AMC6821-Q1
PRODUCTION DATA
This mode works as a fan speed regulator that maintains the speed at a programmable target value. It works only when the TACH measurement is enabled (bit 2 of 0x02 = 1). When the bits [FDRC1:FDRC0] = [01], the fan works in the software RPM control mode, as shown in Figure 8-15. The host writes the proper value into the TACH Setting Register to set the target fan speed. The actual fan speed is monitored by an on-chip fan speed counter, and the result is stored in the TACH-DATA Register (refer to the Fan Speed Measurement section for more details). The actual speed is compared with the setting value. If there is a difference, the duty cycle is adjusted.
The monitoring and adjustment is made once every second, or once every 250ms, as determined by the TACH-FAST bit of Configuration Register 4 (bit 5, 0x04). Bits [STEP1:STEP0] of the DCY-RAMP Register define the allowed amount of each adjustment. When the difference between the values of the TACH-DATA and TACH Setting Registers are equal to or less than 0x000A, the adjustment finishes. 0x000A corresponds to about 1.8% tolerance for 10,000RPMs, or 0.9% for 5000RPMs. This measurement architecture is illustrated in Figure 8-16.
In practice, the selected target speed must be not too low to operate the fan. When the TACH-MODE bit (bit 1 of 0x02) is cleared ('0'), the duty cycle of PWM-Out is forced to 30% when the calculated desired value of duty cycle is less than 30%. Therefore, the TACH setting must be not greater than the value corresponding to the RPM for 30% duty cycle. When TACH mode = '1', the TACH setting must not be greater than the value corresponding to the allowed minimum RPM at which the fan runs properly.