JAJSHW6A september   2019  – august 2023 BQ21061

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts ( INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good ( PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Trademarks
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY CHARGE TIMERS
tMAXCHG Charge safety timer Programmable range 180 720 min
tPRECHG Precharge safety timer 0.25 * tMAXCHG
WATCHDOG TIMERS
tWATCHDOG_SW SW Watchdog timer 25 50 s
tHW_RESET_WD HW reset watchdog timer HWRESET_14S_WD = 1 14 s
LDO
tON_LDO Turn ON time 100mA load, to 90% VLDO 500 µs
tOFF_LDO Turn OFF time 100mA load, to 10% VLDO 30 µs
tPMID_LDO_DELAY Delay between PMID and LDO enable during power up Startup 20 ms
PUSHBUTTON TIMERS (/MR)
tWAKE1 WAKE1 Timer. Timer for Ship Mode wake. MR_WAKE1_TIMER = 0 106 125 144 ms
tWAKE2 WAKE2 Timer. Time from /MR falling edge to INT being asserted. MR_WAKE2_TIMER = 1 1.7 2 2.3 s
tRESET_WARN RESET_WARN Timer. Time prior to HW RESET or entering Shipmode with /MR press MR_RESET_WARN = 01 0.85 1 1.15 s
tHW_RESET Time from /MR Falling edge to HW RESET or PMID falling for Shipmode Entry MR_HW_RESET = 01 6.8 8 9.2 s
tRESTART(AUTOWAKE) RESTART Timer. Time from /MR HW Reset to PMID power up AUTOWAKE = 01 1.05 1.2 1.35 s
PROTECTION
tDGL_SLP Deglitch time for supply rising above VSLP + VSLP_HYS 120 µs
tDGL_OVP Deglitch time for VOVP Threshold VIN falling below VOVP 32 ms
tDGL_OCP Battery OCP deglitch time 30 µs
tREC_SC Recovery time, BAT Short Circuit during Discharge Mode 250 ms
tRETRY_SC Retry window for PMID or BAT short circuit recovery 2 s
tDGL_SHTDWN Deglitch time, Thermal shutdown TJ rising above TSHUTDOWN 10 µs
I2C INTERFACE
tWATCHDOG I2C interface reset timer for host When enabled 50 s
tI2CRESET I2C interface inactive reset timer 500 ms
INPUT PINS (/CE and /LP)
tLP_EXIT_I2C Time for device to exit Low-power mode and allow I2C communication VIN = 0V. 1 ms