JAJSJE2A july   2020  – april 2023 BQ21062

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Linear Charger and Power Path
        1. 9.3.1.1 Battery Charging Process
        2. 9.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM)
        4. 9.3.1.4 Battery Supplement Mode
      2. 9.3.2  Protection Mechanisms
        1. 9.3.2.1 Input Over-Voltage Protection
        2. 9.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 9.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 9.3.2.4 Battery Short and Over Current Protection
        5. 9.3.2.5 PMID Short Circuit
      3. 9.3.3  VDD LDO
      4. 9.3.4  Load Switch/LDO Output and Control
      5. 9.3.5  PMID Power Control
      6. 9.3.6  System Voltage (PMID) Regulation
      7. 9.3.7  MR Wake and Reset Input
        1. 9.3.7.1 MR Wake or Short Button Press Functions
        2. 9.3.7.2 MR Reset or Long Button Press Functions
      8. 9.3.8  14-Second Watchdog for HW Reset
      9. 9.3.9  Faults Conditions and Interrupts ( INT)
        1. 9.3.9.1 Flags and Fault Condition Response
      10. 9.3.10 Power Good ( PG) Pin
      11. 9.3.11 External NTC Monitoring (TS)
        1. 9.3.11.1 TS Thresholds
      12. 9.3.12 I2C Interface
        1. 9.3.12.1 F/S Mode Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Ship Mode
      2. 9.4.2 Low Power
      3. 9.4.3 Active Battery
      4. 9.4.4 Charger/Adapter Mode
      5. 9.4.5 Power-Up/Down Sequencing
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input (IN/PMID) Capacitors
        2. 10.2.2.2 VDD, LDO Input and Output Capacitors
        3. 10.2.2.3 TS
        4. 10.2.2.4 Recommended Passive Components
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFP|20
サーマルパッド・メカニカル・データ

9.5.1 I2C Registers

Table 9-6 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 9-6 should be considered as reserved locations and the register contents should not be modified.

Table 9-6 I2C Registers
AddressAcronymRegister NameSection
0x0STAT0Charger Status 0Go
0x1STAT1Charger Status 1Go
0x2STAT2Status 2Go
0x3FLAG0Charger Flags 0Go
0x4FLAG1Charger Flags 1Go
0x5FLAG2Flags 2Go
0x6FLAG3Timer FlagsGo
0x7MASK0Interrupt Masks 0Go
0x8MASK1Interrupt Masks 1Go
0x9MASK2Interrupt Masks 2Go
0xAMASK3Interrupt Masks 3Go
0x12VBAT_CTRLBattery Voltage ControlGo
0x13ICHG_CTRLFast Charge Current ControlGo
0x14PCHRGCTRLPre-Charge Current ControlGo
0x15TERMCTRLTermination Current ControlGo
0x16BUVLOBattery UVLO and Current Limit ControlGo
0x17CHARGERCTRL0Charger Control 0Go
0x18CHARGERCTRL1Charger Control 1Go
0x19ILIMCTRLInput Corrent Limit ControlGo
0x1DLDOCTRLLDO ControlGo
0x30MRCTRLMR ControlGo
0x35ICCTRL0IC Control 0Go
0x36ICCTRL1IC Control 1Go
0x37ICCTRL2IC Control 2Go
0x40TS_READTS ReadGo
0x58TS_FAULT_MEASTS Fault MeasurementGo
0x61TS_FASTCHGCTRLTS Charge ControlGo
0x62TS_COLDTS Cold ThresholdGo
0x63TS_COOLTS Cool ThresholdGo
0x64TS_WARMTS Warm ThresholdGo
0x65TS_HOTTS Hot ThresholdGo
0x6FDEVICE_IDDevice IDGo

Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for access types in this section.

Table 9-7 I2C Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCC
R		to Clear
Read
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

9.5.1.1 STAT0 Register (Address = 0x0) [reset = X]

STAT0 is shown in Figure 9-16 and described in Table 9-8.

Return to Summary Table.

Figure 9-16 STAT0 Register
76543210
RESERVEDCHRG_CV_STATCHARGE_DONE_STATIINLIM_ACTIVE_STATRESERVEDVINDPM_ACTIVE_STATTHERMREG_ACTIVE_STATVIN_PGOOD_STAT
R-XR-XR-XR-XR-XR-XR-XR-X
Table 9-8 STAT0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRXReserved
6CHRG_CV_STATRXConstant Voltage Charging Mode (Taper Mode) Status

1b0 = Not Active

1b1 = Active

5CHARGE_DONE_STATRXCharge Done Status

1b0 = Not Active

1b1 = Active

4IINLIM_ACTIVE_STATRXInput Current Limit Status

1b0 = Not Active

1b1 = Active

3RESERVEDRXReserved
2VINDPM_ACTIVE_STATRXVINDPM Status

1b0 = Not Active

1b1 = Active

1THERMREG_ACTIVE_STATRXThermal Regulation Status

1b0 = Not Active

1b1 = Active

0VIN_PGOOD_STATRXVIN Power Good Status .

1b0 = Not Good

1b1 = VIN > VUVLO and VIN > VBAT + VSLP and VIN < VOVP

9.5.1.2 STAT1 Register (Address = 0x1) [reset = X]

STAT1 is shown in Figure 9-17 and described in Table 9-9.

Return to Summary Table.

Figure 9-17 STAT1 Register
76543210
VIN_OVP_FAULT_STATRESERVEDBAT_OCP_FAULT_STATBAT_UVLO_FAULT_STATTS_COLD_STATTS_COOL_STATTS_WARM_STATTS_HOT_STAT
R-XR-XR-XR-XR-XR-XR-XR-X
Table 9-9 STAT1 Register Field Descriptions
BitFieldTypeResetDescription
7VIN_OVP_FAULT_STATRXVIN Overvoltage Status

1b0 = Not Active

1b1 = Active

6RESERVEDRXReserved
5BAT_OCP_FAULT_STATRXBattery Over-Current Protection Status

1b0 = Not Active

1b1 = Active

4BAT_UVLO_FAULT_STATRXBattery voltage below BATUVLO Level Status

1b0 = VBAT > VBATUVLO

1b1 = VBAT < VBATUVLO

3TS_COLD_STATRXTS Cold Status - VTS > VCOLD (charging suspended)

1b0 = Not Active

1b1 = Active

2TS_COOL_STATRXTS Cool Status - VCOOL < VTS < VCOLD (charging current reduced by value set by TS_Registers)

1b0 = Not Active

1b1 = Active

1TS_WARM_STATRXTS Warm - VWARM > VTS >VHOT (charging voltage reduced by value set by TS_Registers)

1b0 = Not Active

1b1 = Active

0TS_HOT_STATRXTS Hot Status - VTS < VHOT (charging suspended)

1b0 = Not Active

1b1 = Active

9.5.1.3 STAT2 Register (Address = 0x2) [reset = X]

STAT2 is shown in Figure 9-18 and described in Table 9-10.

Return to Summary Table.

Figure 9-18 STAT2 Register
76543210
RESERVEDTS_OPEN_STAT
R-XR-XR-XR-XR-XR-X
Table 9-10 STAT2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRXReserved
3-1RESERVEDRXReserved
0TS_OPEN_STATRXTS Open Status

1b0 = VTS < VOPEN

1b1 = VTS > VOPEN

9.5.1.4 FLAG0 Register (Address = 0x3) [reset = 0x0]

FLAG0 is shown in Figure 9-19 and described in Table 9-11.

Return to Summary Table.

Clear on Read

Figure 9-19 FLAG0 Register
76543210
RESERVEDCHRG_CV_FLAGCHARGE_DONE_FLAGIINLIM_ACTIVE_FLAGRESERVEDVINDPM_ACTIVE_FLAGTHERMREG_ACTIVE_FLAGVIN_PGOOD_FLAG
RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0
Table 9-11 FLAG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRC1b0Reserved
6CHRG_CV_FLAGRC1b0Constant Voltage Charging Mode (Taper Mode) Flag

1b0 = CV Mode Entry not detected

1b1 = CV Mode Entry detected

5CHARGE_DONE_FLAGRC1b0Charge Done Flag

1b0 = Charge Done (Termination) not detected

1b1 = Charge Done (Termination) detected

4IINLIM_ACTIVE_FLAGRC1b0Input Current Limit Flag

1b0 = Input Current Limit not detected

1b1 = Input Current Limit detected

3RESERVEDRC1b0Reserved
2VINDPM_ACTIVE_FLAGRC1b0VINDPM Flag

1b0 = VINDPM operation not detected

1b1 = VIINDPM operation detected

1THERMREG_ACTIVE_FLAGRC1b0Thermal Regulation Flag

1b0 = Thermal Regulation not detected

1b1 = Thermal Regulation detected

0VIN_PGOOD_FLAGRC1b0VIN Power Good Flag . Interrupt will not be sent if device powers up with VIN_PGOOD condition and VBAT < VBATUVLO

1b0 = No change in VIN Power Good Status

1b1 = Change in VIN Power Good Status detected.

9.5.1.5 FLAG1 Register (Address = 0x4) [reset = 0x0]

FLAG1 is shown in Figure 9-20 and described in Table 9-12.

Return to Summary Table.

Clear on Read

Figure 9-20 FLAG1 Register
76543210
VIN_OVP_FAULT_FLAGRESERVEDBAT_OCP_FAULT_FLAGBAT_UVLO_FAULT_FLAGTS_COLD_FLAGTS_COOL_FLAGTS_WARM_FLAGTS_HOT_FLAG
RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0
Table 9-12 FLAG1 Register Field Descriptions
BitFieldTypeResetDescription
7VIN_OVP_FAULT_FLAGRC1b0VIN Over Voltage Fault Flag

1b0 = No overvoltage condition detected

1b1 = VIN overvoltage condition detected

6RESERVEDRC1b0Reserved
5BAT_OCP_FAULT_FLAGRC1b0Battery Over Current Protection Flag

1b0 = No Battery Over Current condition detected

1b1 = Battery Over Current condition detected

4BAT_UVLO_FAULT_FLAGRC1b0Battery Under Voltage Flag

1b0 = Battery below BATUVLO condition detected

1b1 = No Battery below BATUVLO condition detected

3TS_COLD_FLAGRC1b0TS Cold Region Entry Flag

1b0 = TS Cold Region Entry not detected

1b1 = TS Cold Region Entry detected

2TS_COOL_FLAGRC1b0TS Cool Region Entry Flag

1b0 = TS Cool Region Entry not detected

1b1 = TS Co0l Region Entry detected

1TS_WARM_FLAGRC1b0TS Warm Region Entry Flag

1b0 = TS Warm Region Entry not detected

1b1 = TS Warm Region Entry detected

0TS_HOT_FLAGRC1b0TS Hot Region Entry Flag

1b0 = TS Hot Region Entry not detected

1b1 = TS Hot Region Entry detected

9.5.1.6 FLAG2 Register (Address = 0x5) [reset = 0x0]

FLAG2 is shown in Figure 9-21 and described in Table 9-13.

Return to Summary Table.

Clear on Read

Figure 9-21 FLAG2 Register
76543210
RESERVEDTS_OPEN_FLAG
RC-1b0RC-1b0RC-1b0RC-1b0RC-3b000RC-1b0
Table 9-13 FLAG2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRXReserved
3-1RESERVEDRC3b000Reserved
0TS_OPEN_FLAGRC1b0TS Open Flag

1b0 = No TS Open fault detected

1b1 = TS Open fault detected

9.5.1.7 FLAG3 Register (Address = 0x6) [reset = 0x0]

FLAG3 is shown in Figure 9-22 and described in Table 9-14.

Return to Summary Table.

Clear on Read

Figure 9-22 FLAG3 Register
76543210
RESERVEDWD_FAULT_FLAGSAFETY_TMR_FAULT_FLAGLDO_OCP_FAULT_FLAGRESERVEDMRWAKE1_TIMEOUT_FLAGMRWAKE2_TIMEOUT_FLAGMRRESET_WARN_FLAG
RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0RC-1b0
Table 9-14 FLAG3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRC1b0Reserved
6WD_FAULT_FLAGRC1b0Watchdog Fault Flag

1b0 = Watchdog Timer not expired

1b1 = Watchdog Timer expired

5SAFETY_TMR_FAULT_FLAGRC1b0Safety Timer Fault Flag

1b0 = Safety Timer not expired

1b1 = Safety Timer Expired

4LDO_OCP_FAULT_FLAGRC1b0LDO Over Current Fault

1b0 = LDO Normal

1b1 = LDO Over current fault detected

2MRWAKE1_TIMEOUT_FLAGRC1b0MR Wake 1 Timer Flag

1b0 = MR Wake 1 timer not expired

1b1 = MR Wake 1 timer expired

1MRWAKE2_TIMEOUT_FLAGRC1b0MR Wake 2 Timer Flag

1b0 = MR Wake 2 timer not expired

1b1 = MR Wake 2 timer expired

0MRRESET_WARN_FLAGRC1b0MR Reset Warn Timer Flag

1b0 = MR Reset Warn timer not expired

1b1 = MR Reset Warn timer expired

9.5.1.8 MASK0 Register (Address = 0x7) [reset = 0x0]

MASK0 is shown in Figure 9-23 and described in Table 9-15.

Return to Summary Table.

Figure 9-23 MASK0 Register
76543210
RESERVEDCHRG_CV_MASKCHARGE_DONE_MASKIINLIM_ACTIVE_MASKRESERVEDVINDPM_ACTIVE_MASKTHERMREG_ACTIVE_MASKVIN_PGOOD_MASK
R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0
Table 9-15 MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W1b0Reserved

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

6CHRG_CV_MASKR/W1b0Mask for CHRG_CV interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

5CHARGE_DONE_MASKR/W1b0Mask for CHARGE_DONE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

4IINLIM_ACTIVE_MASKR/W1b0Mask for IINLIM_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

3RESERVEDR/W1b0Reserved
2VINDPM_ACTIVE_MASKR/W1b0Mask for VINDPM_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

1THERMREG_ACTIVE_MASKR/W1b0Mask for THERMREG_ACTIVE interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

0VIN_PGOOD_MASKR/W1b0Mask for VIN_PGOOD interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.9 MASK1 Register (Address = 0x8) [reset = 0x0]

MASK1 is shown in Figure 9-24 and described in Table 9-16.

Return to Summary Table.

Figure 9-24 MASK1 Register
76543210
VIN_OVP_FAULT_MASKRESERVEDBAT_OCP_FAULT_MASKBAT_UVLO_FAULT_MASKTS_COLD_MASKTS_COOL_MASKTS_WARM_MASKTS_HOT_MASK
R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0
Table 9-16 MASK1 Register Field Descriptions
BitFieldTypeResetDescription
7VIN_OVP_FAULT_MASKR/W1b0Mask for VIN_OVP_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

6RESERVEDR/W1b0Reserved
5BAT_OCP_FAULT_MASKR/W1b0Mask for BAT_OCP_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

4BAT_UVLO_FAULT_MASKR/W1b0Mask for BAT_UVLO_FAULT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

3TS_COLD_MASKR/W1b0Mask for TS_COLD interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

2TS_COOL_MASKR/W1b0Mask for TS_COOL interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

1TS_WARM_MASKR/W1b0Mask for TS_WARM interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

0TS_HOT_MASKR/W1b0Mask for TS_HOT interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]

MASK2 is shown in Figure 9-25 and described in Table 9-17.

Return to Summary Table.

Figure 9-25 MASK2 Register
76543210
RESERVEDTS_OPEN_MASK
R/W-1b0R/W-1b1R/W-1b1R/W-1b1R/W-3b000R/W-1b1
Table 9-17 MASK2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3-1RESERVEDR/W3b000Reserved
0TS_OPEN_MASKR/W1b1Mask for TS_OPEN Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]

MASK3 is shown in Figure 9-26 and described in Table 9-18.

Return to Summary Table.

Figure 9-26 MASK3 Register
76543210
RESERVEDWD_FAULT_MASKSAFETY_TMR_FAULT_MASKLDO_OCP_FAULT_MASKRESERVEDMRWAKE1_TIMEOUT_MASKMRWAKE2_TIMEOUT_MASKMRRESET_WARN_MASK
R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W-1b0
Table 9-18 MASK3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W1b0Reserved
6WD_FAULT_MASKR/W1b0Mask for WD_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

5SAFETY_TMR_FAULT_MASKR/W1b0Mask for SAFETY_TIMER_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

4LDO_OCP_FAULT_MASKR/W1b0Mask for LDO_OCP_FAULT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

3RESERVEDR/W1b0Reserved
2MRWAKE1_TIMEOUT_MASKR/W1b0Mask for MRWAKE1_TIMEOUT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

1MRWAKE2_TIMEOUT_MASKR/W1b0Mask for MRWAKE2_TIMEOUT Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

0MRRESET_WARN_MASKR/W1b0Mask for MRRESET_WARN Interrupt

1b0 = Interrupt Not Masked

1b1 = Interrupt Masked

9.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]

VBAT_CTRL is shown in Figure 9-27 and described in Table 9-19.

Return to Summary Table.

Figure 9-27 VBAT_CTRL Register
76543210
RESERVEDVBAT_REG_6:0
R/W-1b0R/W-7b0111100
Table 9-19 VBAT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W1b0Reserved
6-0VBAT_REG_6:0R/W7b0111100Battery Regulation Voltage (4.2 V default)
VBATREG = 3.6 V + VBAT_REG code x 10 mV
If a value greater than 4.6 V is written, the setting will go to 4.6 V

9.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x36]

ICHG_CTRL is shown in Figure 9-28 and described in Table 9-20.

Return to Summary Table.

Figure 9-28 ICHG_CTRL Register
76543210
ICHG_7:0
R/W-8b00110110
Table 9-20 ICHG_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-0ICHG_7:0R/W8b00110110Fast Charge Current (67.5 mA default)
Fast Charge Current = 1.25 mA x ICHG code (ICHARGE_RANGE = 0)
Fast Charge Current = 2.5 mA x ICHG code (ICHARGE_RANGE = 1)

9.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x7]

PCHRGCTRL is shown in Figure 9-29 and described in Table 9-21.

Return to Summary Table.

Figure 9-29 PCHRGCTRL Register
76543210
ICHARGE_RANGERESERVEDIPRECHG_4:0
R/W-1b0R/W-2b00R/W-5b00111
Table 9-21 PCHRGCTRL Register Field Descriptions
BitFieldTypeResetDescription
7ICHARGE_RANGER/W1b0Charge Current Step

1b0 = 1.25 mA step (318.75 mA max charge current)

1b1 = 2.5 mA step (500 mA max charge current)

6-5RESERVEDR/W2b00Reserved
4-0IPRECHG_4:0R/W5b00111Pre-Charge Current (8.75 mA default)
Pre-Charge Current = 1.25 mA x IPRECHG code (ICHARGE_RANGE = 0)
Pre-Charge Current = 2.5 mA x IPRECHG code (ICHARGE_RANGE = 1)

9.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]

TERMCTRL is shown in Figure 9-30 and described in Table 9-22.

Return to Summary Table.

Figure 9-30 TERMCTRL Register
76543210
RESERVEDITERM_4:0TERM_DISABLE
R/W-2b00R/W-5b01010R/W-1b0
Table 9-22 TERMCTRL Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W2b00Reserved
5-1ITERM_4:0R/W5b01010Termination Current (10% of ICHRG default)
Programmable Range = 1% to 31% of ICHRG

5b00000 = Do not Use

5b00001 = 1% of ICHRG

5b00010 = 2% of ICHRG

5b00100 = 4% of ICHRG

5b01000 = 8% of ICHRG

5b10000 = 16% of ICHRG

0TERM_DISABLER/W1b0Termination Disable

1b0 = Termination Enabled

1b1 = Termination Disabled

9.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x3]

BUVLO is shown in Figure 9-31 and described in Table 9-23.

Return to Summary Table.

Figure 9-31 BUVLO Register
76543210
RESERVEDVLOWV_SELIBAT_OCP_ILIM_1:0BUVLO_2:0
R/W-2b00R/W-1b0R/W-2b00R/W-3b011
Table 9-23 BUVLO Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W2b00Reserved
5VLOWV_SELR/W1b0Pre-charge to Fast Charge Threshold

1b0 = 3.0 V

1b1 = 2.8 V

4-3IBAT_OCP_ILIM_1:0R/W2b00Battery Over-Current Protection Threshold

2b00 = 1200 mA

2b01 = 1500 mA

2b10 = Disabled

2b11 = Disabled

2-0BUVLO_2:0R/W3b011Battery UVLO Voltage

3b000 = 3.0 V

3b001 = 3.0 V

3b010 = 3.0 V

3b011 = 2.8 V

3b100 = 2.6 V

3b101 = 2.4 V

3b110 = 2.2 V

3b111 = Disabled

9.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x92]

CHARGERCTRL0 is shown in Figure 9-32 and described in Table 9-24.

Return to Summary Table.

Figure 9-32 CHARGERCTRL0 Register
76543210
TS_ENTS_CONTROL_MODEVRH_THRESHWATCHDOG_DISABLE2XTMR_ENSAFETY_TIMER_LIMIT_1:0RESERVED
R/W-1b1R/W-1b0R/W-1b0R/W-1b1R/W-1b0R/W-2b01R/W-1b0
Table 9-24 CHARGERCTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7TS_ENR/W1b1TS Function Enable

1b0 = TS function disabled (Only charge control is disabled. TS_OPEN detection and TS ADC monitoring remain enabled)

1b1 = TS function enabled

6TS_CONTROL_MODER/W1b0TS Function Control Mode

1b0 = Custom (JEITA)

1b1 = Disable charging on HOT/COLD Only

5VRH_THRESHR/W1b0Recharge Voltage Threshold

1b0 = 140 mV

1b1 = 200 mV

4WATCHDOG_DISABLER/W1b1Watchdog Timer Disable

1b0 = Watchdog timer enabled

1b1 = Watchdog timer disabled

32XTMR_ENR/W1b0Enable 2X Safety Timer

1b0 = The timer is not slowed at any time

1b1 = The timer is slowed by 2x when in any control other than CC or CV

2-1SAFETY_TIMER_LIMIT_1:0R/W2b01Charger Safety Timer

2b00 = 3 Hr Fast Charge

2b01 = 6 Hr Fast Charge

2b10 = 12 Hr Fast Charge

2b11 = Disabled

0RESERVEDR/W1b0Reserved

9.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0x32]

CHARGERCTRL1 is shown in Figure 9-33 and described in Table 9-25.

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Figure 9-33 CHARGERCTRL1 Register
76543210
VINDPM_DISVINPDM_2:0RESERVEDTHERM_REG_2:0
R/W-1b0R/W-3b011R/W-1b1R/W-3b010
Table 9-25 CHARGERCTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7VINDPM_DISR/W1b0Disable VINDPM Function

1b0 = VINDPM Enabled

1b1 = VINDPM Disabled

6-4VINPDM_2:0R/W3b011VINDPM Level Selection

3b000 = 4.2 V

3b001 = 4.3 V

3b010 = 4.4 V

3b011 = 4.5 V

3b100 = 4.6 V

3b101 = 4.7 V

3b110 = 4.8 V

3b111 = 4.9 V

3RESERVEDR/W1b1Reserved
2-0THERM_REG_2:0R/W3b010Thermal Charge Current Foldback Threshold

3b000 = 80°C

3b001 = 85°C

3b010 = 90°C

3b011 = 95°C

3b100 = 100°C

3b101 = 105°C

3b110 = 110°C

3b111 = Disabled

9.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x1]

ILIMCTRL is shown in Figure 9-34 and described in Table 9-26.

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Figure 9-34 ILIMCTRL Register
7 6 5 4 3 2 1 0
RESERVED ILIM_2:0
R/W-5b00000 R/W-3b001
Table 9-26 ILIMCTRL Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R/W 5b00000 Reserved
2-0 ILIM_2:0 R/W 3b001 Input Current Limit Level Selection

3b000 = 50 mA

3b001 = 100 mA

3b010 = 150 mA

3b011 = 200 mA

3b100 = 300 mA

3b101 = 400 mA

3b110 = 500 mA

3b111 = 600 mA

9.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0x32]

LDOCTRL is shown in Figure 9-35 and described in Table 9-27.

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Figure 9-35 LDOCTRL Register
76543210
EN_LS_LDOVLDO_4:0LDO_SWITCH_CONFGRESERVED
R/W-1b0R/W-5b01100R/W-1b1R/W-1b0
Table 9-27 LDOCTRL Register Field Descriptions
BitFieldTypeResetDescription
7EN_LS_LDOR/W1b0LS/LDO Enable

1b0 = Disable LS/LDO

1b1 = Enable LS/LDO

6-2VLDO_4:0R/W5b01100LDO output voltage setting (1.8 V default)
LDO Voltage = 600 mV + VLDO Code x 100 mV
1LDO_SWITCH_CONFGR/W1b1LDO / Load Switch Configuration Select

1b0 = LDO

1b1 = Load Switch

0RESERVEDR/W1b0Reserved

9.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2E]

MRCTRL is shown in Figure 9-36 and described in Table 9-28.

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Figure 9-36 MRCTRL Register
76543210
MR_RESET_VINMR_WAKE1_TIMERMR_WAKE2_TIMERMR_RESET_WARN_1:0MR_HW_RESET_1:0RESERVED
R/W-1b0R/W-1b0R/W-1b1R/W-2b01R/W-2b11R/W-1b0
Table 9-28 MRCTRL Register Field Descriptions
BitFieldTypeResetDescription
7MR_RESET_VINR/W1b0VIN Power Good gated MR Reset Enable

1b0 = Reset sent when /MR reset time is met regardless of VIN state

1b1 = Reset sent when MR reset is met and Vin is valid

6MR_WAKE1_TIMERR/W1b0Wake 1 Timer setting

1b0 = 125 ms

1b1 = 500 ms

5MR_WAKE2_TIMERR/W1b1Wake 2 Timer setting

1b0 = 1 s

1b1 = 2 s

4-3MR_RESET_WARN_1:0R/W2b01MR Reset Warn Timer setting

2b00 = MR_HW_RESET - 0.5 s

2b01 = MR_HW_RESET - 1.0 s

2b10 = MR_HW_RESET - 1.5 s

2b11 = MR_HW_RESET - 2.0 s

2-1MR_HW_RESET_1:0R/W2b11MR HW Reset Timer setting

2b00 = 4 s

2b01 = 8 s

2b10 = 10 s

2b11 = 14 s

0RESERVEDR/W1b0Reserved

9.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x20]

ICCTRL0 is shown in Figure 9-37 and described in Table 9-29.

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Figure 9-37 ICCTRL0 Register
76543210
EN_SHIP_MODERESERVEDAUTOWAKE_1:0RESERVEDGLOBAL_INT_MASKHW_RESETSW_RESET
R/W-1b0R/W-1b0R/W-2b10R/W-1b0R/W-1b0R/W-1b0R/W-1b0
Table 9-29 ICCTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_SHIP_MODER/W1b0Ship Mode Enable

1b0 = Normal operation

1b1 = Enter Ship Mode when VIN is not valid and /MR is high

6RESERVEDR/W1b0Reserved
5-4AUTOWAKE_1:0R/W2b10Auto-wakeup Timer (TRESTART) for /MR HW Reset

2b00 = 0.6 s

2b01 = 1.2 s

2b10 = 2.4 s

2b11 = 5 s

3RESERVEDR/W1b0Reserved
2GLOBAL_INT_MASKR/W1b0Global Interrupt Mask

1b0 = Normal Operation

1b1 = Mask all interrupts

1HW_RESETR/W1b0HW Reset

1b0 = Normal operation

1b1 = HW Reset. Temporarily power down all power rails, except VDD. I2C Register go to default settings.

0SW_RESETR/W1b0SW_Reset

1b0 = Normal operation

1b1 = SW Reset. I2C Registers go to default settings.

9.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]

ICCTRL1 is shown in Figure 9-38 and described in Table 9-30.

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Figure 9-38 ICCTRL1 Register
76543210
MR_LPRESS_ACTION_1:0RESERVEDRESERVEDPG_MODE_1:0PMID_MODE_1:0
R/W-2b00R/W-1b0R/W-1b0R/W-2b00R/W-2b00
Table 9-30 ICCTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-6MR_LPRESS_ACTION_1:0R/W2b00MR Long Press Action

2b00 = HW Reset (Power Cycle)

2b01 = Do nothing

2b10 = Enter Ship Mode

2b11 = Enter Ship Mode

5RESERVEDR/W1b0Reserved
4RESERVEDR/W1b0Reserved
3-2PG_MODE_1:0R/W2b00PG Pin Mode of Operation

2b00 = VIN Power Good. PG pulls to GND when VIN > VUVLO, VIN > VBAT+VSLP and VIN < VIN_OVP.

2b01 = Deglitched Level Shifted /MR. PG is high impedance when the MR input is high, and PG pulls to GND when the MR input is low.

2b1x = General Purpose Open Drain Output. The state of the PG pin is then controlled through the GPO_PG bit, where if GPO_PG is 0 , the PG pin is pulled to GND and if it is 1, the PG pin is in high impedance.

1-0PMID_MODE_1:0R/W2b00PMID Control
Sets how PMID is powered in any state, except Ship Mode.

2b00 = PMID powered from BAT or VIN if present

2b01 = PMID powered from BAT only, even if VIN is present

2b10 = PMID disconnected and left floating

2b11 = PMID disconnected and pulled down.

9.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]

ICCTRL2 is shown in Figure 9-39 and described in Table 9-31.

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Figure 9-39 ICCTRL2 Register
76543210
PMID_REG_CTRL_2:0GPO_PGRESERVEDHWRESET_14S_WDCHARGER_DISABLE
R/W-3b010R/W-1b0R/W-2b00R/W-1b0R/W-1b0
Table 9-31 ICCTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-5PMID_REG_CTRL_2:0R/W3b010System (PMID) Regulation Voltage

3b000 = Battery Tracking

3b001 = 4.4 V

3b010 = 4.5 V

3b011 = 4.6 V

3b100 = 4.7 V

3b101 = 4.8 V

3b110 = 4.9 V

3b111 = Pass-Through (VIN)

4GPO_PGR/W1b0/PG General Purpose Output State Control

1b0 = Pulled Down

1b1 = High Z

3-2RESERVEDR/W2b00Reserved
1HWRESET_14S_WDR/W1b0Enable for 14-second I2C watchdog timer for HW Reset after VIN connection

1b0 = Timer disabled

1b1 = Device will perform HW reset if no I2C transaction is done within 14 s after VIN is present

0CHARGER_DISABLER/W1b0Charge Disable

1b0 = Charge enabled if /CE pin is low

1b1 = Charge disabled

9.5.1.25 TS_READ Register (Address = 0x40) [reset = 0x2]

TS_Read is shown in Figure 9-40 and described in Table 9-32.

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Figure 9-40 TS_READ Register

7

6

5

4

3

2

1

0

INTERVAL

RESERVED

GET_FAULT_ENABLE

RESERVED

RESERVED

R/W-1b0

R-1b0

R/W-1b0

R/W-2b00

R/W-3b010

Table 9-32 TS_READ Register Field Descriptions

Bit

Field

Type

Reset

Description

7

INTERVAL

R/W

1b0Interval rate for TS read in BAT Only operation

1b0 = Manual Read (TS pin checked when GET_FAULT_ENABLE is set)

1b1 = TS pin checked every 1 second

6

RESERVED

R/W

1b0Reserved

5

GET_FAULT_ENABLE

R/W

1b0

TS Fault Read Trigger. Bit goes back to 0 when read is complete

1b0 = Normal Operation

1b1 = Initiate TS Fault read

4-3

RESERVED

R/W

2b00Reserved

2-0

RESERVED

R/W

3b010Reserved

9.5.1.26 TS_FAULT_MEAS Register (Address = 0x58) [reset = 0x0]

TS_FAULT_MEAS is shown in Figure 9-41 and described in Table 9-33.

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Figure 9-41 TS_FAULT_MEAS Register
76543210
ReservedReservedReservedReservedReservedFault_EnableReservedReserved
R/W-1b0R/W-1b0R/W-1b0R/W-1b0R/W- 1b0R/W-1b0R/W-1b0R/W-1b0
Table 9-33 TS_Fault_MEAS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W1b0Reserved
6RESERVEDR/W1b0Reserved
5RESERVEDR/W1b0Reserved
4RESERVEDR/W1b0Reserved
3RESERVEDR/W1b0Reserved
2TS_FAULT_MEAS_ENABLER/W1b0Enable TS Fault Measurement

1b0 = Measurement disabled

1b1 = Measurement enabled

1RESERVEDR/W1b0Reserved
0RESERVEDR/W1b0Reserved

9.5.1.27 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]

TS_FASTCHGCTRL is shown in Figure 9-42 and described in Table 9-34.

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Figure 9-42 TS_FASTCHGCTRL Register
76543210
RESERVEDTS_VBAT_REG__2:0RESERVEDTS_ICHRG_2:0
R/W-1b0R/W-3b011R/W-1b0R/W-3b100
Table 9-34 TS_FASTCHGCTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W1b0Reserved
6-4TS_VBAT_REG__2:0R/W3b011Reduced target battery voltage during Warm

3b000 = No reduction

3b001 = VBAT_REG - 50 mV

3b010 = VBAT_REG - 100 mV

3b011 = VBAT_REG - 150 mV

3b100 = VBAT_REG - 200 mV

3b101 = VBAT_REG - 250 mV

3b110 = VBAT_REG - 300 mV

3b111 = VBAT_REG - 350 mV

3RESERVEDR/W1b0Reserved
2-0TS_ICHRG_2:0R/W3b100Fast charge current when decreased by TS function

3b000 = No reduction

3b001 = 0.875 x ICHG

3b010 = 0.750 x ICHG

3b011 = 0.625 x ICHG

3b100 = 0.500 x ICHG

3b101 = 0.375 x ICHG

3b110 = 0.250 x ICHG

3b111 = 0.125 x ICHG

9.5.1.28 TS_COLD Register (Address = 0x62) [reset = 0x7C]

TS_COLD is shown in Figure 9-43 and described in Table 9-35.

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Figure 9-43 TS_COLD Register
76543210
TS_COLD_7:0
R/W-8b01111100
Table 9-35 TS_COLD Register Field Descriptions
BitFieldTypeResetDescription
7-0TS_COLD_7:0R/W8b01111100TS Cold Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.29 TS_COOL Register (Address = 0x63) [reset = 0x6D]

TS_COOL is shown in Figure 9-44 and described in Table 9-36.

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Figure 9-44 TS_COOL Register
7 6 5 4 3 2 1 0
TS_COOL_7:0
R/W-8b01101101
Table 9-36 TS_COOL Register Field Descriptions
Bit Field Type Reset Description
7-0 TS_COOL_7:0 R/W 8b01101101 TS Cool Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.30 TS_WARM Register (Address = 0x64) [reset = 0x38]

TS_WARM is shown in Figure 9-45 and described in Table 9-37.

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Figure 9-45 TS_WARM Register
76543210
TS_WARM_7:0
R/W-8b00111000
Table 9-37 TS_WARM Register Field Descriptions
BitFieldTypeResetDescription
7-0TS_WARM_7:0R/W8b00111000TS Warm Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.31 TS_HOT Register (Address = 0x65) [reset = 0x38]

TS_HOT is shown in Figure 9-46 and described in Table 9-38.

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Figure 9-46 TS_HOT Register
7 6 5 4 3 2 1 0
TS_HOT_7:0
R/W-8b00111000
Table 9-38 TS_HOT Register Field Descriptions
Bit Field Type Reset Description
7-0 TS_HOT_7:0 R/W 8b00111000 TS Hot Threshold

1b = 4.688 mV

10b = 9.375 mV

100b = 18.75 mV

1000b = 37.5 mV

10000b = 75 mV

100000b = 150 mV

1000000b = 300 mV

10000000b = 600 mV

9.5.1.32 DEVICE_ID Register (Address = 0x6F) [reset = 0x3B]

DEVICE_ID is shown in Figure 9-47 and described in Table 9-39.

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Figure 9-47 DEVICE_ID Register
76543210
DEVICE_ID_7:0
R-8b00111011
Table 9-39 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7-0DEVICE_ID_7:0R8b00111011Device ID

00111011b = BQ21062