SLUSFR2 November   2024 BQ21088

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Pre-Charge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control (SYS_MODE bit control)
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  ILIM Control
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1 Input Overvoltage Protection
        2. 7.3.8.2 Battery Undervoltage Lockout
        3. 7.3.8.3 Battery Overcurrent Protection
        4. 7.3.8.4 System Overvoltage Protection
        5. 7.3.8.5 System Short Protection
        6. 7.3.8.6 Thermal Protection and Thermal Regulation
        7. 7.3.8.7 Safety Timer and Watchdog Timer
      9. 7.3.9  Pushbutton Wake and Reset Input
        1. 7.3.9.1 Pushbutton Wake or Short Button Press Functions
        2. 7.3.9.2 Pushbutton Reset or Long Button Press Functions
      10. 7.3.10 15-Second Timeout for HW Reset
      11. 7.3.11 Hardware Reset
      12. 7.3.12 Software Reset
      13. 7.3.13 Interrupt Indicator (/INT) Pin
      14. 7.3.14 External NTC Monitoring (TS)
        1. 7.3.14.1 TS Biasing and Function
      15. 7.3.15 I2C Interface
        1. 7.3.15.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 I2C Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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発注情報

7.3.14.1 TS Biasing and Function

The device is configured to meet JEITA requirements ora simpler HOT/COLD function only. Additionally, the TS charger control function can be disabled through the TS_EN bit. This will only disable the TS charge action but the faults are still reported based on the TS voltage. To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold,the cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT thresholds in the Electrical Characteristics table. Charging and safety timers are suspended when VTS < VHOT or VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to the value programmed in the TS_Setting register/ bit TS_ICHG_0. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 100 mV or 200 mV based on the value programmed in TS_VRCG_0 bit within the TS_Setting register.

For devices where the TS function is not needed, tie a 10-kΩ resistor to the TS/MR pin.

There is an active voltage clamp present on this device which will prevent the voltage on TS/MR pin from rising above the VTS_CLAMP threshold. This will particularly be ON when the TS/MR pin is floating. The bit TS_OPEN_STAT is set when this clamp is active. This will also be ON regardless of the TS_EN bit. The interrupt is asserted as long as the TS_INT mask is not written.

The bits TS_HOT, TS_COLD, TS_WARM and TS_COOL will allow these thresholds to be adjusted slightly. The hysteresis will also move along with these thresholds. When the TS_WARM condition occurs, the device will lower the battery target regulation voltage by TS_VRCG but will not modify the VBAT_CTRL register.

The TS_ICHG bit will reduce charging current based on the factor described in the register map when the TSMR pin hits a TS_COOL condition. The TREG function will still be based on this reduced threshold.

The TS_VRCG_0 bit will reduce the charging voltage when the TS/MR pin hits the TS_WARM threshold. The factor will be based on the register map.

When the button is detected as a “press” during the charging process, charging will be momentarily suspended until the button is high again. When charging is disabled in any of the TS faults, the trickle charging is also disabled. In a TS fault where the current is reduced (COOL), the trickle charging current is not altered.