JAJSL87H january 2010 – april 2021 BQ24090 , BQ24091 , BQ24092 , BQ24093 , BQ24095
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT | ||||||
| UVLO | Undervoltage lock-out exit | VIN: 0 V → 4 V update based on sim/char | 3.15 | 3.3 | 3.45 | V |
| VHYS_UVLO | Hysteresis on VUVLO_RISE falling | VIN: 4 V→0 V, VUVLO_FALL = VUVLO_RISE –VHYS-UVLO | 175 | 227 | 280 | mV |
| VIN-DT | Input power good detection threshold is VOUT + VIN-DT | (Input power good if VIN > VOUT + VIN-DT); VOUT = 3.6 V, VIN: 3.5 V → 4 V | 30 | 80 | 145 | mV |
| VHYS-INDT | Hysteresis on VIN-DT falling | VOUT = 3.6 V, VIN: 4 V → 3.5 V | 31 | mV | ||
| tDGL(PG_PWR) | Deglitch time on exiting sleep. | Time measured from VIN: 0 V → 5 V 1-μs rise time to PG = low, VOUT = 3.6 V | 45 | μs | ||
| tDGL(PG_NO-PWR) | Deglitch time on VHYS-INDT power down. Same as entering sleep. | Time measured from VIN: 5 V → 3.2 V 1-μs fall time to PG = OC, VOUT = 3.6 V | 29 | ms | ||
| VOVP | Input overvoltage protection threshold | VIN: 5 V → 7 V | 6.5 | 6.65 | 6.8 | V |
| tDGL(OVP-SET) | Input overvoltage blanking time | VIN: 5 V → 7 V | 113 | μs | ||
| VHYS-OVP | Hysteresis on OVP | VIN: 7 V → 5 V | 95 | mV | ||
| tDGL(OVP-REC) | Deglitch time exiting OVP | Time measured from VIN: 7 V → 5 V 1-μs fall-time to PG = LO | 30 | μs | ||
| VIN-DPM | USB/Adaptor low input voltage protection. Restricts lout at VIN-DPM | Feature active in USB Mode; Limit input source current to 50 mA; VOUT = 3.5 V; RISET = 825 Ω | 4.34 | 4.4 | 4.46 | V |
| Feature active in Adaptor Mode; Limit input source current to 50 mA; VOUT = 3.5 V; RISET = 825 Ω | 4.24 | 4.3 | 4.36 | |||
| IIN-USB-CL | USB input I-Limit 100 mA | ISET2 = Float; RISET = 825 Ω | 85 | 92 | 100 | mA |
| USB input I-Limit 500 mA | ISET2 = High; RISET = 825 Ω | 430 | 462 | 500 | ||
| ISET SHORT CIRCUIT TEST | ||||||
| RISET_SHORT | Highest resistor value considered a fault (short). Monitored for Iout>90 mA | Riset: 600 Ω → 250 Ω, IOUT latches off, cycle power to reset. | 280 | 500 | Ω | |
| tDGL_SHORT | Deglitch time transition from ISET short to Iout disable | Clear fault by cycling IN or TS/ BAT_EN | 1 | ms | ||
| IOUT_CL | Maximum OUT current limit Regulation (Clamp) | VIN = 5 V, VOUT = 3.6 V, VISET2 = Low, RISET: 600 Ω → 250 Ω, Iout latches off after tDGL-SHORT | 1.05 | 1.4 | A | |
| BATTERY SHORT PROTECTION | ||||||
| VOUT(SC) | OUT pin short-circuit detection threshold/ precharge threshold | VOUT: 3 V → 0.5 V, no deglitch | 0.75 | 0.8 | 0.85 | V |
| VOUT(SC-HYS) | OUT pin short hysteresis | Recovery ≥ VOUT(SC) + VOUT(SC-HYS); rising, no deglitch | 77 | mV | ||
| IOUT(SC) | Source current to OUT pin during short-circuit detection | 10 | 15 | 20 | mA | |
| QUIESCENT CURRENT | ||||||
| IOUT(PDWN) | Battery current into OUT pin | VIN = 0 V | 1 | μA | ||
| IOUT(DONE) | OUT pin current, charging terminated | VIN = 6 V, VOUT > VOUT(REG) | 6 | |||
| IIN(STDBY) | Standby current into IN pin | TS = LO, VIN ≤ 6 V | 125 | μA | ||
| ICC | Active supply current, IN pin | TS = open, VIN = 6 V, TTDM – no load on OUT pin, VOUT > VOUT(REG), IC enabled | 0.8 | 1.0 | mA | |
| BATTERY CHARGER FAST-CHARGE | ||||||
| VOUT(REG) | Battery regulation voltage (BQ24090/1/2/3) | VIN = 5.5 V, IOUT = 25 mA, (VTS-45°C≤ VTS ≤ VTS-0°C) | 4.16 | 4.2 | 4.23 | V |
| Battery regulation voltage (BQ24095) | VIN = 5.5 V, IOUT = 25 mA | 4.30 | 4.35 | 4.40 | ||
| VO_HT(REG) | Battery hot regulation Voltage, BQ24092/3 | VIN = 5.5 V, IOUT = 25 mA, VTS-60°C≤ VTS ≤ VTS-45°C | 4.02 | 4.06 | 4.1 | V |
| IOUT(RANGE) | Programmed Output fast charge current range | VOUT(REG) > VOUT > VLOWV; VIN = 5 V,
ISET2=Lo, RISET = 540 to 10.8 kΩ | 10 | 1000 | mA | |
| VDO(IN-OUT) | Drop-Out, VIN – VOUT | Adjust VIN down until IOUT = 0.5 A, VOUT = 4.15 V, RISET = 540, ISET2 = Lo (Adaptor Mode); TJ ≤ 100°C | 325 | 520 | mV | |
| IOUT | Output fast charge formula | VOUT(REG) > VOUT > VLOWV; VIN = 5 V, ISET2 = Lo | KISET/RISET | A | ||
| KISET | Fast charge current factor for BQ24090, 91, 92, 93 | RISET = KISET /IOUT; 50 < IOUT < 1000 mA | 510 | 540 | 565 | AΩ |
| RISET = KISET /IOUT; 25 < IOUT < 50 mA | 480 | 527 | 580 | |||
| RISET = KISET /IOUT; 10 < IOUT < 25 mA | 350 | 520 | 680 | |||
| KISET | Fast charge current factor for BQ24095 | RISET = KISET /IOUT; 50 < IOUT < 1000 mA | 510 | 560 | 585 | AΩ |
| RISET = KISET /IOUT; 25 < IOUT < 50 mA | 480 | 557 | 596 | |||
| RISET = KISET /IOUT; 10 < IOUT < 25 mA | 350 | 555 | 680 | |||
| PRECHARGE – SET BY PRETERM PIN | ||||||
| VLOWV | Pre-charge to fast-charge transition threshold | 2.4 | 2.5 | 2.6 | V | |
| tDGL1(LOWV) | Deglitch time on pre-charge to fast-charge transition | 70 | μs | |||
| tDGL2(LOWV) | Deglitch time on fast-charge to pre-charge transition | 32 | ms | |||
| IPRE-TERM | Refer to the Termination Section | |||||
| %PRECHG | Pre-charge current, default setting | VOUT < VLOWV; RISET = 1080 Ω; RPRE-TERM= High Z | 18 | 20 | 22 | %IOUT-CC |
| Pre-charge current formula | RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%) | RPRE-TERM/KPRE-CHG% | ||||
| KPRE-CHG | % Pre-charge Factor | VOUT < VLOWV, VIN = 5 V, RPRE-TERM = 2 k to 10 kΩ; RISET = 1080 Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 20 to 100% | 90 | 100 | 110 | Ω/% |
| VOUT < VLOWV, VIN = 5 V, RPRE-TERM = 1 k to 2 kΩ; RISET = 1080 Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 10% to 20% | 84 | 100 | 117 | Ω/% | ||
| TERMINATION – SET BY PRE-TERM PIN | ||||||
| %TERM | Termination threshold current, default setting | VOUT > VRCH; RISET = 1 k; RPRE-TERM = High Z | 9 | 10 | 11 | %IOUT-CC |
| Termination current threshold Formula | RPRE-TERM = KTERM (Ω/%) × %TERM (%) | RPRE-TERM/ KTERM | ||||
| KTERM | % Term factor | VOUT > VRCH, VIN = 5 V, RPRE-TERM = 2 k to 10 kΩ; RISET = 750 Ω KTERM × %IFAST-CHG, where %IFAST-CHG is 10 to 50% | 182 | 200 | 216 | Ω/% |
| VOUT > VRCH, VIN = 5 V, RPRE-TERM = 1 k to 2 kΩ; RISET = 750 Ω KTERM × %Iset, where %Iset is 5 to 10% | 174 | 199 | 224 | |||
| IPRE-TERM | Current for programming the term. and pre-chg with resistor. ITerm-Start is the initial PRE-TERM current. | RPRE-TERM = 2 k, VOUT = 4.15 V | 71 | 75 | 81 | μA |
| %TERM | Termination current formula | RTERM/ KTERM% | ||||
| tDGL(TERM) | Deglitch time, termination detected | 29 | ms | |||
| ITerm-Start | Elevated PRE-TERM current for, tTerm-Start, during start of charge to prevent recharge of full battery | 80 | 85 | 92 | μA | |
| tTerm-Start | Elevated termination threshold initially active for tTerm-Start | 1.25 | min | |||
| RECHARGE OR REFRESH | ||||||
| VRCH | Recharge detection threshold – normal temp | VIN = 5V, VTS = 0.5 V, VOUT: 4.25 V → VRCH | VO(REG)-0.120 | VO(REG)-0.095 | VO(REG)-0.070 | V |
| Recharge detection threshold – hot temp | VIN = 5 V, VTS = 0.2V, VOUT: 4.15 V → VRCH | VO(REG)-0.130 | VO(REG)-0.105 | VO(REG)-0.080 | V | |
| tDGL1(RCH) | Deglitch time, recharge threshold detected | VIN = 5 V, VTS = 0.5 V, VOUT: 4.25 V → 3.5 V in 1μs; tDGL(RCH) is time to ISET ramp | 29 | ms | ||
| tDGL2(RCH) | Deglitch time, recharge threshold detected in OUT-Detect Mode | VIN = 5 V, VTS = 0.5V, VOUT = 3.5 V inserted; tDGL(RCH) is time to ISET ramp | 3.6 | ms | ||
| BATTERY DETECT ROUTINE | ||||||
| VREG-BD | VOUT reduced regulation during battery detect | VIN = 5 V, VTS = 0.5 V, battery absent | VO(REG)-0.450 | VO(REG)-0.400 | VO(REG)-350 | V |
| IBD-SINK | Sink current during VREG-BD | 6 | 10 | mA | ||
| tDGL(HI/LOW REG) | Regulation time at VREG or VREG-BD | 25 | ms | |||
| VBD-HI | High battery detection threshold | VIN = 5 V, VTS = 0.5 V, battery absent | VO(REG) -0.150 | VO(REG)-0.100 | VO(REG)-0.050 | V |
| VBD-LO | Low battery detection threshold | VIN = 5 V, VTS = 0.5 V, battery absent | VREG-BD +0.50 | VREG-BD +0.1 | VREG-BD +0.15 | V |
| BATTERY CHARGING TIMERS AND FAULT TIMERS | ||||||
| tPRECHG | Pre-charge safety timer value | Restarts when entering pre-charge; always enabled when in pre-charge | 1700 | 1940 | 2250 | s |
| tMAXCH | Charge safety timer value | Clears fault or resets at UVLO, TS/ BAT_EN disable, OUT short, exiting LOWV and refresh | 34000 | 38800 | 45000 | s |
| BATTERY-PACK NTC MONITOR (Note 1); TS pin: 10 k and 100 k NTC | ||||||
| INTC-10k | NTC bias current, BQ24090/2/5 | VTS = 0.3 V | 48 | 50 | 52 | μA |
| INTC-100k | NTC bias current, BQ24091/3 | VTS = 0.3 V | 4.8 | 5.0 | 5.2 | μA |
| INTC-DIS-10k | 10k NTC bias current when Charging is disabled, BQ24090/2/5 | VTS = 0 V | 27 | 30 | 34 | μA |
| INTC-DIS-100k | 100k NTC bias current when Charging is disabled, BQ24091/3 | VTS = 0 V | 4.4 | 5.0 | 5.8 | μA |
| INTC-FLDBK-10k | INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, BQ24090/2/5 | VTS: Set to 1.525 V | 4 | 5 | 6.5 | μA |
| INTC-FLDBK-100k | INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, BQ24091/3 | VTS: Set to 1.525 V | 1.1 | 1.5 | 1.9 | μA |
| VTTDM(TS) | Termination and Timer Disable Mode Threshold – enter | VTS: 0.5 V → 1.7 V; timer held in Reset | 1550 | 1600 | 1650 | mV |
| VHYS-TTDM(TS) | Hysteresis exiting TTDM | VTS: 1.7 V → 0.5 V; timer enabled | 100 | mV | ||
| VCLAMP(TS) | TS maximum voltage clamp | VTS = Open (float) | 1800 | 1950 | 2000 | mV |
| tDGL(TTDM) | Deglitch exit TTDM between states | 57 | ms | |||
| Deglitch enter TTDM between states | 8 | μs | ||||
| VTS_I-FLDBK | TS voltage where INTC is reduce to keep thermistor from entering TTDM | INTC adjustment (90 to 10%; 45 to 6.6 μS) takes place near this spec threshold. VTS: 1.425 V → 1.525 V | 1475 | mV | ||
| CTS | Optional capacitance – ESD | 0.22 | μF | |||
| VTS-0°C | Low temperature CHG pending | Low temp charging to pending; VTS: 1.0 V → 1.5 V | 1205 | 1230 | 1255 | mV |
| VHYS-0°C | Hysteresis at 0°C | Charge pending to low temp charging; VTS: 1.5 V → 1 V | 86 | mV | ||
| VTS-10°C | Low temperature, half charge, BQ24092/3 | Normal charging to low temp charging; VTS: 0.5 V → 1 V | 765 | 790 | 815 | mV |
| VHYS-10°C | Hysteresis at 10°C, BQ24092/3 | Low temp charging to normal CHG; VTS: 1.0 V → 0.5 V | 35 | mV | ||
| VTS-45°C | High temperature at 4.1V | Normal charging to high temp CHG; VTS: 0.5 V → 0.2 V | 263 | 278 | 293 | mV |
| VHYS-45°C | Hysteresis at 45°C | High temp charging to normal CHG; VTS: 0.2 V → 0.5 V | 10.7 | mV | ||
| VTS-60°C | High temperature disable, BQ24092/3 | High temp charge to pending; VTS: 0.2 V → 0.1 V | 170 | 178 | 186 | mV |
| VHYS-60°C | Hysteresis at 60°C, BQ24092/3 | Charge pending to high temp CHG; VTS: 0.1 V → 0.2 V | 11.5 | mV | ||
| tDGL(TS_10C) | Deglitch for TS thresholds: 10C, BQ24092/3 | Normal to cold operation; VTS: 0.6 V → 1 V | 50 | ms | ||
| Cold to normal operation; VTS: 1 V → 0.6 V | 12 | |||||
| tDGL(TS) | Deglitch for TS thresholds: 0/45/60C. | Battery charging | 30 | ms | ||
| VTS-EN-10k | Charge Enable Threshold, (10k NTC) | VTS: 0 V → 0.175 V | 80 | 88 | 96 | mV |
| VTS-DIS_HYS-10k | HYS below VTS-EN-10k to Disable, (10k NTC) | VTS: 0.125 V → 0 V | 12 | mV | ||
| VTS-EN-100k | Charge Enable Threshold, BQ24090/2 | VTS: 0 V → 0.175 V | 140 | 150 | 160 | mV |
| VTS-DIS_HYS-100k | HYS below VTS-EN-100k to Disable, BQ24091/3 | VTS: 0.125 V → 0 V | 50 | mV | ||
| THERMAL REGULATION | ||||||
| TJ(REG) | Temperature regulation limit | 125 | °C | |||
| TJ(OFF) | Thermal shutdown temperature | 155 | °C | |||
| TJ(OFF-HYS) | Thermal shutdown hysteresis | 20 | °C | |||
| LOGIC LEVELS ON ISET2 | ||||||
| VIL | Logic LOW input voltage | Sink 8 μA | 0.4 | V | ||
| VIH | Logic HIGH input voltage | Source 8 μA | 1.4 | V | ||
| IIL | Sink current required for LO | VISET2= 0.4 V | 2 | 9 | μA | |
| IIH | Source current required for HI | VISET2= 1.4 V | 1.1 | 9.5 | μA | |
| VFLT | ISET2 Float voltage | 575 | 900 | 1225 | mV | |
| LOGIC LEVELS ON CHG AND PG | ||||||
| VOL | Output LOW voltage | ISINK = 5 mA | 0.4 | V | ||
| ILEAK | Leakage current into IC | V CHG = 5 V, V PG = 5 V | 1 | μA | ||