The BQ24160/0A/3 contain a D+, D– based adapter detection circuit that is used to program the input current limit for the USB input during DEFAULT mode. D+, D– detection is only performed in DEFAULT mode unless forced by the D+, D–_EN bit in host mode. Writing to register 2 during detection stops the detection routine.

By default the USB input current limit is set to 100 mA. When a voltage higher than UVLO is applied to the USB input, the BQ24160/0A/3 performs a charger source identification to determine if it is connected to an SDP (USB port) or CDP/DCP (dedicated charger). The first step is D+, D- line connection detection as described in BC1.2. Primary detection begins 10 ms after the connection detection complete. The primary detection complies with the method described in BC1.2. During primary detection, the D+, D- lines are tested to determine if the port is an SDP or CDP/DCP. If a CDP/DCP is detected the input current limit is increased to 1.5 A, if an SDP is detected the current limit remains at 100 mA, until changed via the I²C interface. These two steps require at least 90 ms to complete but if they have not completed within 500 ms, the D+, D- detection routine selects 100 mA for the unknown input source. Secondary detection as described in BC1.2 is not performed.

Automatic detection is performed only if V_D+ and V_D– are less than 0.6 V to avoid interfering with the USB transceiver which may also perform D+, D– detection when the system is running normally. However, D+, D– can be initiated at any time by the host by setting the D+, D– EN bit in the Control/Battery Voltage Register to 1. After detection is complete the D+, D– EN bit is automatically reset to 0 and the detection circuitry is disconnected from the D+, D– pins to avoid interference with USB data transfer.

When a command is written to change the input current limit in the I²C, this overrides the current limit selected by D+/D– detection. D+, D– detection has no effect on the IN input.