JAJSGI6C September   2011  – January 2020 BQ24725A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adapter Detect and ACOK Output
      2. 8.4.2  Adapter Over Voltage (ACOVP)
      3. 8.4.3  System Power Selection
      4. 8.4.4  Battery LEARN Cycle
      5. 8.4.5  Enable and Disable Charging
      6. 8.4.6  Automatic Internal Soft-Start Charger Current
      7. 8.4.7  High Accuracy Current Sense Amplifier
      8. 8.4.8  Charge Timeout
      9. 8.4.9  Converter Operation
      10. 8.4.10 Continuous Conduction Mode (CCM)
      11. 8.4.11 Discontinuous Conduction Mode (DCM)
      12. 8.4.12 Input Over Current Protection (ACOC)
      13. 8.4.13 Charge Over Current Protection (CHGOCP)
      14. 8.4.14 Battery Over Voltage Protection (BATOVP)
      15. 8.4.15 Battery Shorted to Ground (BATLOWV)
      16. 8.4.16 Thermal Shutdown Protection (TSHUT)
      17. 8.4.17 EMI Switching Frequency Adjust
      18. 8.4.18 Inductor Short, MOSFET Short Protection
    5. 8.5 Register Maps
      1. 8.5.1 Battery-Charger Commands
      2. 8.5.2 Setting Charger Options
        1. Table 3. Charge Options Register (0x12H)
      3. 8.5.3 Setting the Charge Current
        1. Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
      4. 8.5.4 Setting the Charge Voltage
        1. Table 5. Charge Voltage Register (0x15H)
      5. 8.5.5 Setting Input Current
        1. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical System with Two NMOS Selector
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Negative Output Voltage Protection
          2. 9.2.1.2.2 Reverse Input Voltage Protection
          3. 9.2.1.2.3 Reduce Battery Quiescent Current
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input Capacitor
          6. 9.2.1.2.6 Output Capacitor
          7. 9.2.1.2.7 Power MOSFETs Selection
          8. 9.2.1.2.8 Input Filter Design
          9. 9.2.1.2.9 BQ24725A Design Guideline
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Simplified System without Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VVCC_OP VCC Input voltage operating range 4.5 24 V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG Battery voltage range 1.024 19.2 V
VBAT_REG_ACC Charge voltage regulation accuracy ChargeVoltage() = 0x41A0H 16.716 16.8 16.884 V
-0.5% 0.5%
ChargeVoltage() = 0x3130H 12.529 12.592 12.655 V
–0.5% 0.5%
ChargeVoltage() = 0x20D0H 8.350 8.4 8.45 V
–0.6% 0.6%
ChargeVoltage() = 0x1060H 4.163 4.192 4.221 V
–0.7% 0.7%
CHARGE CURRENT REGULATION
VIREG_CHG_RNG Charge current regulation differential voltage range VIREG_CHG = VSRP - VSRN 0 81.28 mV
ICHRG_REG_ACC Charge current regulation accuracy 10mΩ current sensing resistor ChargeCurrent() = 0x1000H 3973 4096 4219 mA
–3% 3%
ChargeCurrent() = 0x0800H 1946 2048 2150 mA
–5% 5%
ChargeCurrent() = 0x0200H 410 512 614 mA
–20% 20%
ChargeCurrent() = 0x0100H 172 256 340 mA
–33% 33%
ChargeCurrent() = 0x0080H 64 128 192 mA
–50% 50%
INPUT CURRENT REGULATION
VIREG_DPM_RNG Input current regulation differential voltage range VIREG_DPM = VACP – VACN 0 80.64 mV
IDPM_REG_ACC Input current regulation accuracy 10mΩ current sensing resistor InputCurrent() = 0x1000H 3973 4096 4219 mA
–3% 3%
InputCurrent() = 0x0800H 1946 2048 2150 mA
–5% 5%
InputCurrent() = 0x0400H 870 1024 1178 mA
–15% 15%
InputCurrent() = 0x0200H 384 512 640 mA
–25% 25%
INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER
VACP/N_OP Input common mode range Voltage on ACP/ACN 4.5 24 V
VSRP/N_OP Output common mode range Voltage on SRP/SRN 0 19.2 V
VIOUT IOUT output voltage range 0 3.3 V
IIOUT IOUT output current 0 1 mA
AIOUT Current sense amplifier gain V(ICOUT)/V(SRP-SRN) or V(ACP-ACN) 20 V/V
VIOUT_ACC Current sense output accuracy V(SRP-SRN) or V(ACP-ACN) = 40.96mV –2% 2%
V(SRP-SRN) or V(ACP-ACN) = 20.48mV –4% 4%
V(SRP-SRN) or V(ACP-ACN) = 10.24mV –15% 15%
V(SRP-SRN) or V(ACP-ACN) = 5.12mV –20% 20%
V(SRP-SRN) or V(ACP-ACN) = 2.56mV –33% 33%
V(SRP-SRN) or V(ACP-ACN) = 1.28mV –50% 50%
CIOUT_MAX Maximum output load capacitance For stability with 0 to 1mA load 100 pF
REGN REGULATOR
VREGN_REG REGN regulator voltage VVCC > 6.5V, VACDET > 0.6V (0-45mA load) 5.5 6 6.5 V
IREGN_LIM REGN current limit VREGN = 0V, VVCC > UVLO charge enabled and not in TSHUT 50 75 mA
VREGN = 0V, VVCC > UVLO charge disabled or in TSHUT 7 14 mA
CREGN REGN output capacitor required for stability ILOAD = 100µA to 50mA 1 µF
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
UVLO Under voltage rising threshold VVCC rising 3.5 3.75 4 V
Under voltage hysteresis, falling VVCC falling 340 mV
FAST DPM COMPARATOR (FAST_DPM)
VFAST_DPM Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage across input sense resistor rising edge 103% 107% 111%
QUIESCENT CURRENT
IBAT_BATFET_OFF Battery BATFET OFF STATE Current, BATFET off,
ISRP + ISRN + IPHASE + IACP + IACN 		VVBAT = 16.8V, VCC disconnect from battery, BATFET charge pump off, BATFET turns off, TJ = 0 to 85°C 5 µA
IBAT_BATFET_ON Battery BATFET ON STATE Current, BATFET on,
ISRP + ISRN + IPHASE + IVCC + IACP + IACN 		VVBAT = 16.8V, VCC connect from battery, BATFET charge pump on, BATFET turns on, TJ = 0 to 85°C 25 µA
ISTANDBY Standby quiescent current, IVCC + IACP + IACN VVCC > UVLO, VACDET > 0.6V, charge disabled,
TJ = 0 to 85°C		 0.65 0.8 mA
IAC_NOSW Adapter bias current during charge,
IVCC + IACP + IACN 		VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, no switching, TJ = 0 to 85°C		 1.5 3 mA
IAC_SW Adapter bias current during charge,
IVCC + IACP + IACN 		VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, switching, MOSFET Sis412DN		 10 mA
ACOK COMPARATOR
VACOK_RISE ACOK rising threshold VVCC > UVLO, VACDET rising 2.376 2.4 2.424 V
VACOK_FALL_HYS ACOK falling hysteresis VVCC> UVLO, VACDET falling 35 55 75 mV
VACOK_RISE_DEG ACOK rising deglitch (Specified by design) VVCC> UVLO, VACDET rising above 2.4V,
First time OR ChargeOption() bit [15] = 0 		100 150 200 ms
VVCC> UVLO, VACDET rising above 2.4V,
(NOT First time) AND ChargeOption() bit [15] = 1 (Default)		 0.9 1.3 1.7 s
VWAKEUP_RISE WAKEUP detect rising threshold VVCC> UVLO, VACDET rising 0.57 0.8 V
VWAKEUP_FALL WAKEUP detect falling threshold VVCC> UVLO, VACDET falling 0.3 0.51 V
VCC to SRN COMPARATOR (VCC_SRN)
VVCC-SRN_FALL VCC-SRN falling threshold VVCC falling towards VSRN 70 125 200 mV
VVCC-SRN _RHYS VCC-SRN rising hysteresis VVCC rising above VSRN 100 150 200 mV
ACN to SRN COMPARATOR (ACN_SRN)
VACN-SRN_FALL ACN to BAT falling threshold VACN falling towards VSRN 120 200 280 mV
VACN-SRN_RHYS ACN to BAT rising hysteresis VACN rising above VSRN 40 80 120 mV
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)(1)
VIFAULT_HI_RISE ACP to PHASE rising threshold ChargeOption() bit [8] = 1 (Default) 450 750 1200 mV
ChargeOption() bit [8] = 0 Disable function
LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)(1)
VIFAULT_LOW_RISE PHASE to GND rising threshold ChargeOption() bit [7] = 0 (Default) 70 135 220 mV
ChargeOption() bit [7] = 1 140 230 340
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV ACDET over voltage rising threshold VACDET rising 3.05 3.15 3.25 V
VACOV_HYS ACDET over voltage falling hysteresis VACDET falling 50 75 100 mV
INPUT OVER-CURRENT COMPARATOR (ACOC)(1)
VACOC Adapter over current rising threshold with respect to input current limit, voltage across input sense resistor rising edge ChargeOption() bit [1] = 1 (Default) 300% 333% 366%
ChargeOption() bit [1] = 0 Disable function
VACOC_min Min ACOC threshold clamp voltage ChargeOption() Bit [1] = 1 (333%),
InputCurrent () = 0x0400H (10.24mV)		 40 45 50 mV
VACOC_max Max ACOC threshold clamp voltage ChargeOption() Bit [1] = 1 (333%),
InputCurrent () = 0x1F80H (80.64mV)		 135 150 165 mV
tACOC_DEG ACOC deglitch time (Specified by design) Voltage across input sense resistor rising to disable charge 2.3 4.2 6.6 ms
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
VOVP_RISE Over voltage rising threshold as percentage of VBAT_REG VSRN rising 103% 104% 106%
VOVP_FALL Over voltage falling threshold as percentage of VBAT_REG VSRN falling 102%
CHARGE OVER-CURRENT COMPARATOR (CHG_OCP)
VOCP_RISE Charge over current rising threshold, measure voltage drop across current sensing resistor ChargeCurrent()=0x0xxxH 54 60 66 mV
ChargeCurrent()=0x1000H – 0x17C0H 80 90 100 mV
ChargeCurrent()=0x1800 H– 0x1FC0H 110 120 130 mV
CHARGE UNDER-CURRENT COMPARATOR (CHG_UCP)
VUCP_FALL Charge under-current falling threshold VSRP falling towards VSRN 1 5 9 mV
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
VLL_FALL Light load falling threshold Measure the voltage drop across current sensing resistor 1.25 mV
VLL_RISE_HYST Light load rising hysteresis 1.25 mV
BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]
VBATDEPL_FALL Battery depletion falling threshold, percentage of voltage regulation limit, VSRN falling ChargeOption() bit [12:11] = 00 55.53% 59.19% 63.5%
ChargeOption() bit [12:11] = 01 58.68% 62.65% 67.5%
ChargeOption() bit [12:11] = 10 62.17% 66.55% 71.5%
ChargeOption() bit [12:11] = 11 (Default) 66.06% 70.97% 77%
VBATDEPL_RHYST Battery depletion rising hysteresis, VSRN rising ChargeOption() bit [12:11] = 00 225 305 400 mV
ChargeOption() bit [12:11] = 01 240 325 430 mV
ChargeOption() bit [12:11] = 10 255 345 450 mV
ChargeOption() bit [12:11] = 11 (Default) 280 370 490 mV
tBATDEPL_RDEG Battery Depletion Rising Deglitch (Specified by design) Delay to turn off ACFET and turn on BATFET during LEARN cycle 600 ms
BATTERY LOWV COMPARATOR (BAT_LOWV)
VBATLV_FALL Battery LOWV falling threshold VSRN falling 2.4 2.5 2.6 V
VBATLV_RHYST Battery LOWV rising hysteresis VSRN rising 200 mV
IBATLV Battery LOWV charge current limit 10 mΩ current sensing resistor 0.5 A
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT Thermal shutdown rising temperature Temperature rising 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20 °C
ILIM COMPARATOR
VILIM_FALL ILIM as CE falling threshold VILIM falling 60 75 90 mV
VILIM_RISE ILIM as CE rising threshold VILIM rising 90 105 120 mV
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold 0.8 V
VIN_ HI Input high threshold 2.1 V
IIN_ LEAK Input bias current V = 7 V –1 1 μA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO Output saturation voltage 5 mA drain current 500 mV
IOUT_ LEAK Leakage current V = 7 V –1 1 μA
ANALOG INPUT (ACDET, ILIM)
IIN_ LEAK Input bias current V = 7 V –1 1 μA
PWM OSCILLATOR
FSW PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz
FSW+ PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz
FSW– PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz
BATFET GATE DRIVER (BATDRV)
IBATFET BATDRV charge pump current limit 40 60 µA
VBATFET Gate drive voltage on BATFET VBATDRV - VSRN when VSRN > UVLO 5.5 6.1 6.5 V
RBATDRV_LOAD Minimum load resistance between BATDRV and SRN 500 kΩ
RBATDRV_OFF BATDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
ACFET GATE DRIVER (ACDRV)
IACFET ACDRV charge pump current limit 40 60 μA
VACFET Gate drive voltage on ACFET VACDRV–VCMSRC when VVCC> UVLO 5.5 6.1 6.5 V
RACDRV_LOAD Minimum load resistance between ACDRV and CMSRC 500 kΩ
RACDRV_OFF ACDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ
VACFET_LOW ACDRV Turn-Off when Vgs voltage is low (Specified by design) 5.9 V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance VBTST – VPH = 5.5 V, I = 10 mA 6 10 Ω
RDS_HI_OFF High side driver turn-off resistance VBTST – VPH = 5.5 V, I = 10 mA 0.65 1.3 Ω
VBTST_REFRESH Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 3.85 4.3 4.7 V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON Low side driver turn-on resistance VREGN = 6 V, I = 10 mA 7.5 12 Ω
RDS_LO_OFF Low side driver turn-off resistance VREGN = 6 V, I = 10 mA 0.9 1.4 Ω
PWM DRIVER TIMING
tLOW_HIGH Driver dead time from low side to high side 20 ns
tHIGH_LOW Driver dead time from high side to low side 20 ns
INTERNAL SOFT START
ISTEP Soft start current step In CCM mode 10mΩ current sensing resistor 64 mA
tSTEP Soft start current step time 240 μs
SMBus TIMING CHARACTERISTICS
tR SCLK/SDATA rise time 1 μs
tF SCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 μs
tW(L) SCLK Pulse Width Low 4.7 μs
tSU(STA) Setup time for START condition 4.7 μs
tH(STA) START condition hold time after which first clock pulse is generated 4 μs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 μs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout(2) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 01(3) 35 44 53 s
Watchdog timeout period, ChargeOption() bit [14:13] = 10(3) 70 88 105 s
Watchdog timeout period, ChargeOption() bit [14:13] = 11(3) (Default) 140 175 210 s
(1) User can adjust threshold via SMBus ChargeOption() REG0x12.
(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(3) User can adjust threshold via SMBus ChargeOption() REG0x12.