JAJSGI6C September   2011  – January 2020 BQ24725A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adapter Detect and ACOK Output
      2. 8.4.2  Adapter Over Voltage (ACOVP)
      3. 8.4.3  System Power Selection
      4. 8.4.4  Battery LEARN Cycle
      5. 8.4.5  Enable and Disable Charging
      6. 8.4.6  Automatic Internal Soft-Start Charger Current
      7. 8.4.7  High Accuracy Current Sense Amplifier
      8. 8.4.8  Charge Timeout
      9. 8.4.9  Converter Operation
      10. 8.4.10 Continuous Conduction Mode (CCM)
      11. 8.4.11 Discontinuous Conduction Mode (DCM)
      12. 8.4.12 Input Over Current Protection (ACOC)
      13. 8.4.13 Charge Over Current Protection (CHGOCP)
      14. 8.4.14 Battery Over Voltage Protection (BATOVP)
      15. 8.4.15 Battery Shorted to Ground (BATLOWV)
      16. 8.4.16 Thermal Shutdown Protection (TSHUT)
      17. 8.4.17 EMI Switching Frequency Adjust
      18. 8.4.18 Inductor Short, MOSFET Short Protection
    5. 8.5 Register Maps
      1. 8.5.1 Battery-Charger Commands
      2. 8.5.2 Setting Charger Options
        1. Table 3. Charge Options Register (0x12H)
      3. 8.5.3 Setting the Charge Current
        1. Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
      4. 8.5.4 Setting the Charge Voltage
        1. Table 5. Charge Voltage Register (0x15H)
      5. 8.5.5 Setting Input Current
        1. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical System with Two NMOS Selector
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Negative Output Voltage Protection
          2. 9.2.1.2.2 Reverse Input Voltage Protection
          3. 9.2.1.2.3 Reduce Battery Quiescent Current
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input Capacitor
          6. 9.2.1.2.6 Output Capacitor
          7. 9.2.1.2.7 Power MOSFETs Selection
          8. 9.2.1.2.8 Input Filter Design
          9. 9.2.1.2.9 BQ24725A Design Guideline
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Simplified System without Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Adapter Detect and ACOK Output

The BQ24725A uses an ACOK comparator to determine the source of power on VCC pin, either from the battery or adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage.

The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be pulled to external rail under the following conditions:

  • VVCC > UVLO;
  • 2.4V < VACDET < 3.15V (not in ACOVP condition, nor in low input voltage condition);
  • VVCC–VSRN > 275mV (not in sleep mode);

The first time after IC POR always gives 150ms ACOK rising edge delay no matter what the ChargeOption register value is. Only after the ACDET pin voltage is pulled below 2.4V (but not below 0.6V, which resets the IC and forces the next ACOK rising edge deglitch time to be 1.3s) and the ACFET has been turned off at least one time, the 1.3s (or 150ms) delay time is effective for the next time the ACDET pin voltage goes above 2.4V. To change this option, the VCC pin voltage must above UVLO, and the ACDET pin voltage must be above 0.6V which enables the IC SMBus communication and sets ChargeOption() bit[15] to 0 which sets the next ACOK rising deglitch time to be 150ms. The purpose of the default 1.3s rising edge deglitch time is to turn off the ACFET long enough when the ACDET pin is pulled below 2.4V by excessive system current, such as over current or short circuit.