JAJSHJ9A June   2019  – January 2021 BQ25125

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Ship Mode
        1. 9.3.1.1 Ship Mode Entry and Exit
      2. 9.3.2  High Impedance Mode
      3. 9.3.3  Active Battery Only Connected
      4. 9.3.4  Voltage Based Battery Monitor
      5. 9.3.5  Sleep Mode
      6. 9.3.6  Input Voltage Based Dynamic Power Management (VIN(DPM))
      7. 9.3.7  Input Overvoltage Protection and Undervoltage Status Indication
      8. 9.3.8  Battery Charging Process and Charge Profile
      9. 9.3.9  Battery Supplement Mode
      10. 9.3.10 Default Mode
      11. 9.3.11 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
      12. 9.3.12 Input Current Limit Programming by External Components (ILIM)
      13. 9.3.13 Charge Current Programming by External Components (ISET)
      14. 9.3.14 Safety Timer
      15. 9.3.15 External NTC Monitoring (TS)
      16. 9.3.16 Thermal Protection
      17. 9.3.17 Typical Application Power Dissipation
      18. 9.3.18 Status Indicators ( PG and INT)
      19. 9.3.19 Chip Disable ( CD)
      20. 9.3.20 Buck (PWM) Output
      21. 9.3.21 Load Switch / LDO Output and Control
      22. 9.3.22 Manual Reset Timer and Reset Output ( MR and RESET)
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1  Status and Ship Mode Control Register
      2. 9.6.2  Faults and Faults Mask Register
      3. 9.6.3  TS Control and Faults Masks Register
      4. 9.6.4  Fast Charge Control Register
      5. 9.6.5  Termination/Pre-Charge Register
      6. 9.6.6  Battery Voltage Control Register
      7. 9.6.7  SYS VOUT Control Register
      8. 9.6.8  Load Switch and LDO Control Register
      9. 9.6.9  Push-button Control Register
      10. 9.6.10 ILIM and Battery UVLO Control Register
      11. 9.6.11 Voltage Based Battery Monitor Register
      12. 9.6.12 VIN_DPM and Timers Register
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Default Settings
        2. 10.2.2.2 Choose the Correct Inductance and Capacitance
        3. 10.2.2.3 Calculations
          1. 10.2.2.3.1 Program the Fast Charge Current (ISET)
          2. 10.2.2.3.2 Program the Input Current Limit (ILIM)
          3. 10.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)
          4. 10.2.2.3.4 TS Resistors (TS)
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 Charger Curves
        2. 10.2.3.2 SYS Output Curves
        3. 10.2.3.3 Load Switch and LDO Curves
        4. 10.2.3.4 LS/LDO Output Curves
        5. 10.2.3.5 Timing Waveforms Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 High Impedance Mode

High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are in a low power or sleep state. The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the LS/LDO output has been enabled through I2C prior to entering Hi-Z mode, it will stay enabled. The CD pin is used to put the device in a high-impedance mode when battery is present and VIN < VUVLO. Drive CD high to enable the device and enter active battery operation when VIN is not valid. When the HZ_MODE bit is written by the host, the I2C interface is disabled if only battery is present. To resume I2C, the CD pin must be toggled. If the supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the /CD pin to resume I2C communication.. The functionality of the pin is shown in Table 9-1.

Table 9-1 CD, State Table
CD, STATEVIN < VUVLOVIN > VUVLO
LHi-ZCharge Enabled
HActive BatteryCharge Disabled