JAJSQV7 july   2023 BQ25173-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power Up from Input Source
        1. 7.3.1.1 ISET Pin Detection
      2. 7.3.2 Supercapacitor Regulation Voltage
      3. 7.3.3 Supercapacitor Charging Profile
      4. 7.3.4 Status Outputs (PG, STAT)
        1. 7.3.4.1 Power Good Indicator (PG Pin)
        2. 7.3.4.2 Charging Status Indicator (STAT)
      5. 7.3.5 Protection Features
        1. 7.3.5.1 Input Overvoltage Protection (VIN OVP)
        2. 7.3.5.2 Output Overcurrent Protection (OUT OCP)
        3. 7.3.5.3 Thermal Regulation and Thermal Shutdown (TREG and TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown or Undervoltage Lockout (UVLO)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Standby Mode
      4. 7.4.4 Fault Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1s Supercapacitor Charger Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 4s Supercapacitor Charger Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions


GUID-20230221-SS0I-S8PP-P606-8GZ8NBTF7LJ9-low.svg

Figure 5-1 DRC VSON Package 10-Pin (Top View)
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME

NO.

IN

 1 P Input power. Connect to external DC supply. Bypass IN with at least 1-μF capacitor to GND, placed close to the IC.

ISET

 2

I

 Programs the device fast-charge current, ICHG. External resistor from ISET to GND defines fast-charge current value. Expected range is 30 kΩ (10 mA) to 375 Ω (800 mA). ICHG = KISET / RISET.
CE 3 I Active low charge enable pin. Charging is enabled when CE pin is low. IC remains in Shutdown mode and charging is disabled when CE pin is high. An internal pulldown resistor (RPD_CE) enables the IC by default if this pin is floating.
NC 4 - No connect pin, leave floating
GND 5 – Ground pin
NC 6 - No connect pin, leave floating
STAT 7 O Open-drain charger status indication output. Connect to pullup rail with a 10-kΩ resistor. LOW indicates VOUT has reached 98% of the programmable regulation voltage, VREG. HIGH indicates charge in progress.
PG 8 O Open-drain charger power-good output. Connect to pullup rail with a 10-kΩ resistor. PG goes LOW when VIN > VIN_LOWV and VOUT + VSLEEPZ < VIN < VIN_OV.
FB 9 I Programs the supercapacitor regulation voltage, VREG. Use a feedback divider not exceeding 1 MΩ from VOUT to GND to set the regulation voltage. The bottom of the resistor divider network can be connected to PG for reduced power consumption when the input is removed (for VREG ≤ 5 V).
OUT 10 P Supercapacitor connection. System load may be connected in parallel with supercapacitor. Bypass OUT with at least 1-μF capacitor to GND, placed close to the IC.
Thermal Pad — P Exposed pad beneath the IC for heat dissipation. Solder thermal pad to the board with vias connecting to solid GND plane.
(1) I = Input, O = Output, P = Power