At the beginning of each charge cycle mode (Precharge or Fast Charge), the device starts the respective mode safety timer. If charging has not terminated before the programmed safety time, t_MAXCHG expires or the device does not exit the precharge mode before t_PRECHG expires, charging is disabled. The precharge safety timer, t_PRECHG, is 25% of t_MAXCHG. When a safety timer fault occurs, a single 128-us pulse is sent to the /INT pin and the STAT and FAULT bits of the status registers are updated. The /CE pin, charge enable bit, or the input power must be toggled in order to clear the safety timer.

If the safety timer has expired, the device will produce an interrupt and update the SAFETY_TMR_FAULT_FLAG bit on the register map. The safety timer duration is programmable using the SAFETY_TIMER_1:0 bits. When the safety timer is active, changing the safety timer duration resets the safety timer. The device also contains a 2XTMR_EN bit that doubles the safety timer duration to prevent premature safety timer expiration when the charge current is reduced by a high load on SYS (DPM operation- causing VDPPM to be enabled), VINDPM, thermal regulation, or a NTC (JEITA) condition. When 2XTMR_ENbit is set, the timer is allowed to run at half speed when any loop is active other than CC or CV. In the event where during CC mode the battery voltage drops to push the charger into precharge mode, (due to a large load on battery, thermal events, and so forth) the safety timer will reset counting through precharge and then resetting the fast charge safety timer. If the device entered battery supplement mode while in precharge, CC or CV mode, while the charger is not disabled, the device will suspend the safety timer till the charging can resume back again. This prevents the safety timer from resetting when a supplement condition is caused.

In addition to the safety timer, the device contains a watchdog timer that monitors the host through the I²C interface. The watchdog timer is enabled by default and may be disabled by the host through an I²C transaction. Once the initial transaction is received, the watchdog timer is started. The watchdog timer is reset by any transaction by the host using the I²C interface. If the watchdog timer expires without a reset from the I²C interface, all R/W registers are reset to the default values. Watchdog timer can be set through the WATCHDOG_SEL_1:0 bits either on battery only mode or when adapter is present.

Watchdog can be disabled by writing the disable bit through I²C.