JAJSGP9G October   2011  – August 2023 BQ25504

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Maximum Power Point Tracking
      2. 8.3.2 Battery Undervoltage Protection
      3. 8.3.3 Battery Overvoltage Protection
      4. 8.3.4 Battery Voltage in Operating Range (VBAT_OK Output)
      5. 8.3.5 Nano-Power Management and Efficiency
    4. 8.4 Device Functional Modes
      1. 8.4.1 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS))
      2. 8.4.2 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN, VIN_DC > VIN(DC) and EN = LOW )
      3. 8.4.3 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Storage Element Selection
      2. 9.1.2 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. 9.1.3.1 VREF_SAMP Capacitance
        2. 9.1.3.2 VIN_DC Capacitance
        3. 9.1.3.3 VSTOR Capacitance
        4. 9.1.3.4 Additional Capacitance on VSTOR or VBAT
    2. 9.2 Typical Applications
      1. 9.2.1 Solar Application Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TEG Application Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 MPPT Disabled, Low Impedance Source Application Circuit
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
      2. 12.1.2 Zip Files
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.3.3 Application Curves

GUID-31B5956C-33D6-44D5-A231-73A14390A81C-low.png
VIN_DC = low impedance voltage source = 1.5 V
VBAT = VSTOR = 100 µF
VSTOR = 500 Ω resistor
Figure 9-16 Startup
GUID-9A9CA439-AFCD-4D1D-9697-078468715B9E-low.png
VIN_DC = low impedance voltage source = 1.5 V )
VBAT = VSTOR = 100 µF
VSTOR = open to 75 Ω to open resistive load (IL = load current on VSTOR
Figure 9-18 40 mA Load Transient on VSTOR
GUID-E2BB7970-DA36-44F3-9908-ECB605FD49A0-low.png
VIN_DC = low impedance voltage source = 1.5 V
VBAT = VSTOR = 100 µF
VSTOR artificially ramped from 0 V to 3.3 V to 0 V using a power amp driven by a function generator
Figure 9-20 VBAT_OK Operation
GUID-CBA9F8AC-38EB-4683-A810-265DE7597E72-low.png
VIN_DC = low impedance voltage source = 1.5 V
VBAT = VSTOR = 100 µF
VSTOR = 330 Ω resistive load (IL = inductor current)
Figure 9-17 Boost Charger Operational Waveforms
GUID-D5635559-FC1C-4C5E-BF23-9043214FA955-low.png
VIN_DC = low impedance voltage source = 1.5 V
VBAT = VSTOR = 100 µF
Figure 9-19 VRDIV Operation