JAJSDT3A march   2017  – march 2023 BQ25601

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up from Battery without Input Source
      3. 9.3.3 Power Up from Input Source
        1. 9.3.3.1 Power Up REGN Regulation
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection
          1. 9.3.3.3.1 PSEL Pins Sets Input Current Limit in BQ25601
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Converter Power Up
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Host Mode and Standalone Power Management
        1. 9.3.5.1 Host Mode and Default Mode in BQ25601
      6. 9.3.6 Power Path Management
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
        5. 9.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 9.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
        7. 9.3.7.7 Charging Safety Timer
      8. 9.3.8 Protections
        1. 9.3.8.1 Voltage and Current Monitoring in Converter Operation
          1. 9.3.8.1.1 Voltage and Current Monitoring in Buck Mode
            1. 9.3.8.1.1.1 Input Overvoltage (ACOV)
            2. 9.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.3.8.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.8.2.1 VBUS Soft Start
          2. 9.3.8.2.2 VBUS Output Protection
          3. 9.3.8.2.3 Boost Mode Overvoltage Protection
        3. 9.3.8.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.8.3.1 Thermal Protection in Buck Mode
          2. 9.3.8.3.2 Thermal Protection in Boost Mode
        4. 9.3.8.4 Battery Protection
          1. 9.3.8.4.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.8.4.2 Battery Overdischarge Protection
          3. 9.3.8.4.3 System Overcurrent Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Narrow VDC Architecture
      2. 9.4.2 Dynamic Power Management
      3. 9.4.3 Supplement Mode
      4. 9.4.4 Shipping Mode and QON Pin
        1. 9.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 9.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 9.4.4.3 BATFET Full System Reset
        4. 9.4.4.4 QON Pin Operations
      5. 9.4.5 Status Outputs ( PG, STAT, INT )
        1. 9.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
        2. 9.4.5.2 Charging Status Indicator (STAT)
        3. 9.4.5.3 Interrupt to Host ( INT)
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Target Address and Data Direction Bit
        6. 9.5.1.6 Single Read and Write
        7. 9.5.1.7 Multi-Read and Multi-Write
    6. 9.6 Register Maps
      1. 9.6.1  REG00
      2. 9.6.2  REG01
      3. 9.6.3  REG02
      4. 9.6.4  REG03
      5. 9.6.5  REG04
      6. 9.6.6  REG05
      7. 9.6.7  REG06
      8. 9.6.8  REG07
      9. 9.6.9  REG08
      10. 9.6.10 REG09
      11. 9.6.11 REG0A
      12. 9.6.12 REG0B
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBUS Battery discharge current (BAT, SW, SYS) in buck mode VBAT = 4.5 V, VBUS < VAC-UVLOZ, leakage between BAT and VBUS, TJ< 85°C 5 µA
IBAT Battery discharge current (BAT) in buck mode VBAT = 4.5 V, HIZ Mode or No VBUS, I2C disabled, BATFET Disabled. TJ < 85°C 17 33 µA
IBAT Battery discharge current (BAT, SW, SYS) VBAT = 4.5 V, HIZ Mode or No VBUS, I2C Disabled, BATFET Enabled. TJ < 85°C 58 85 µA
IVBUS_HIZ Input supply current (VBUS) in buck mode VVBUS = 5 V, High-Z Mode, No battery 37 50 µA
IVBUS_HIZ Input supply current (VBUS) in buck mode VVBUS = 12 V, High-Z Mode, No battery 68 90 µA
IVBUS Input supply current (VBUS) in buck mode VVBUS = 12 V, VVBUS > VVBAT, converter not switching 1.5 3 mA
IVBUS Input supply current (VBUS) in buck mode VVBUS > VUVLO, VVBUS > VVBAT, converter switching, VBAT = 3.8V, ISYS = 0A 3 mA
IBOOST Battery Discharge Current in boost mode VBAT = 4.2 V, boost mode, IVBUS = 0 A, converter switching 3 mA
VBUS, VAC AND BAT PIN POWER-UP
VBUS_OP VBUS operating range VVBUS rising 3.9 13.5 V
VVAC_UVLOZ VBUS for active I2C, no battery

Sense VAC pin voltage

 VVAC rising 3.3 3.6 V
VVAC_UVLOZ_HYS I2C active hysteresis VAC falling from above VVAC_UVLOZ 300 mV
VVAC_PRESENT One of the conditions to turn on REGN VVAC rising 3.65 3.9 V
VVAC_PRESENT_HYS One of the conditions to turn on REGN VVAC falling 500 mV
VSLEEP Sleep mode falling threshold (VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT ≤ VREG, VAC falling 15 60 110 mV
VSLEEPZ Sleep mode rising threshold (VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT ≤ VREG, VAC rising 115 220 340 mV
VVAC_OV_RISE VAC 6.5-V Overvoltage rising threshold VAC rising; OVP (REG06[7:6]) = '01' 6.1 6.4 6.7 V
VVAC_OV_RISE VAC 10.5-V Overvoltage rising threshold VAC rising, OVP (REG06[7:6]) = '10' 10.35 10.9 11.5 V
VVAC_OV_RISE VAC 14-V Overvoltage rising threshold VAC rising, OVP (REG06[7:6]) = '11' 13.5 14.2 14.85 V
VVAC_OV_HYS VAC 6.5-V Overvoltage hysteresis VAC falling, OVP (REG06[7:6]) = '01' 320 mV
VVAC_OV_HYS VAC 10.5-V Overvoltage hysteresis VAC falling, OVP (REG06[7:6]) = '10' 250 mV
VVAC_OV_HYS VAC 14-V Overvoltage hysteresis VAC falling, OVP (REG06[7:6]) = '11' 300 mV
VBAT_UVLOZ BAT for active I2C, no adapter VBAT rising 2.5 V
VBAT_DPL_FALL Battery Depletion Threshold VBAT falling 2.2 2.6 V
VBAT_DPL_RISE Battery Depletion Threshold VBAT rising 2.35 2.8 V
VBAT_DPL_HYST Battery Depletion rising hysteresis VBAT rising 180 mV
VBUSMIN_FALL Bad adapter detection falling threshold VBUS falling 3.75 3.9 4.0 V
VBUSMIN_HYST Bad adapter detection hysteresis 80 mV
IBADSRC Bad adapter detection current source Sink current from VBUS to GND 30 mA
POWER-PATH
VSYS_MIN System regulation voltage VBAT < SYS_MIN[2:0] = 101, BATFET Disabled (REG07[5] = 1) 3.5 3.68 V
VSYS System Regulation Voltage ISYS = 0 A, VVBAT > VSYS_MIN, VVBAT = 4.400 V, BATFET disabled (REG07[5] = 1) VBAT + 50 mV V
VSYSMAX Maximum DC system voltage output ISYS = 0 A, , Q4 off, VVBAT≤ 4.400 V, VVBAT > VSYS_MIN = 3.5V 4.4 4.45 4.48 V
RON(RBFET) Top reverse blocking MOSFET on-resistance between VBUS and PMID - Q1 -40°C≤ TA ≤ 125°C 45 mΩ
RON(HSFET) Top switching MOSFET on-resistance between PMID and SW - Q2 VREGN = 5 V , -40°C≤ TA ≤ 125°C 62 mΩ
RON(LSFET) Bottom switching MOSFET on-resistance between SW and GND - Q3 VREGN = 5 V , -40°C≤ TA ≤ 125°C 71 mΩ
VFWD BATFET forward voltage in supplement mode 30 mV
RON(BAT-SYS) SYS-BAT MOSFET on-resistance QFN package, Measured from BAT to SYS, VBAT = 4.2V, TJ = 25°C 19.5 24 mΩ
RON(BAT-SYS) SYS-BAT MOSFET on-resistance QFN package, Measured from BAT to SYS, VBAT = 4.2V, TJ = –40 - 125°C 19.5 30 mΩ
BATTERY CHARGER
VBATREG_RANGE Charge voltage program range 3.856 4.624 V
VBATREG_STEP Charge voltage step 32 mV
VBATREG Charge voltage setting VREG (REG04[7:3]) = 4.208 V (01011), V, –40 ≤ TJ ≤ 85°C 4.187 4.208 4.229 V
VREG (REG04[7:3]) = 4.352 V (01111), V, –40 ≤ TJ ≤ 85°C 4.330 4.352 4.374 V
VBATREG_ACC Charge voltage setting accuracy VBAT = 4.208 V or VBAT = 4.352 V, –40 ≤ TJ ≤ 85°C –0.5% 0.5%
ICHG_REG_RANGE Charge current regulation range 0 3000 mA
ICHG_REG_STEP Charge current regulation step 60 mA
ICHG_REG Charge current regulation setting ICHG = 240 mA, VVBAT = 3.1V or VVBAT = 3.8 V 0.216 0.24 0.264 A
ICHG_REG_ACC Charge current regulation accuracy ICHG = 240 mA, VVBAT = 3.1 V or VVBAT = 3.8 V –10% 10%
ICHG_REG Charge current regulation setting ICHG = 720 mA, VVBAT = 3.1 V or VVBAT = 3.8 V 0.685 0.720 0.755 A
ICHG_REG Charge current regulation accuracy ICHG_REG = 720 mA, VBAT = 3.1 V or VBAT = 3.8 V -5% 5%
IPRECHG Precharge current regulation IPRECHG[3:0] = '0010' = 180 mA 153 171 189 mA
IPRECHG_ACC Precharge current regulation accuracy IPRECHG[3:0] = '0010' = 180 mA –15 5 %
VBATLOWV_FALL Battery LOWV falling threshold ICHG = 240 mA 2.7 2.8 2.9 V
VBATLOWV_RISE Battery LOWV rising threshold Pre-charge to fast charge 3.0 3.12 3.24 V
ICHG_REG Charge current regulation setting ICHG = 1.38 A, VVBAT = 3.1 V or VVBAT = 3.8 V 1.311 1.380 1.449 A
ICHG_REG_ACC Charge current regulation accuracy ICHG = 720 mA or ICHG = 1.38 A, VVBAT = 3.1 V or VVBAT = 3.8 V –5% 5%
ITERM Termination current regulation ICHG > 780 mA, ITERM[3:0] = '0010' = 180 mA, VVBAT = 4.208 V 150 180 216 mA
ITERM_ACC Termination current regulation accuracy ICHG > 780 mA, , ITERM[3:0] = '0010' = 180 mA, VVBAT = 4.208 V -16.7% 20%
ITERM Termination current regulation ICHG ≤ 780 mA, , ITERM[3:0] = '0010' = 180 mA 162 180 192 mA
ITERM_ACC Termination current regulation accuracy ICHG ≤ 780 mA, , ITERM[3:0] = '0010' = 180 mA -10% 10%
ITERM Termination current regulation ICHG = 600 mA, ITERM[3:0] = '0000' = 60 mA, VBAT = 4.208 V 45 60 75 mA
ITERM_ACC Termination current regulation accuracy ICHG = 600 mA, ITERM[3:0] = '0000' = 60 mA, VBAT = 4.208 V –25% 25%
VSHORT Battery short voltage VBAT falling 1.85 2 2.15 V
VSHORTZ Battery short voltage VBAT rising 2.15 2.25 2.35 V
ISHORT Battery short current VBAT < VSHORTZ 70 90 110 mA
VRECHG Recharge Threshold below VBAT_REG VBAT falling, REG04[0] = 0 90 120 150 mV
VRECHG Recharge Threshold below VBAT_REG VBAT falling, REG04[0] = 1 200 230 265 mV
ISYSLOAD System discharge load current VSYS = 4.2 V 30 mA
INPUT VOLTAGE AND CURRENT REGULATION
VINDPM Input voltage regulation limit VINDPM (REG06[3:0] = 0000) = 3.9 V 3.78 3.95 4.1 V
VINDPM_ACC Input voltage regulation accuracy –3% 5%
VINDPM Input voltage regulation limit VINDPM (REG06[3:0] = 0110) = 4.4 V 4.268 4.4 4.532 V
VINDPM_ACC Input voltage regulation accuracy –3% 3%
VDPM_VBAT Input voltage regulation limit tracking VBAT VINDPM = 3.9V, VDPM_VBAT_TRACK = 300mV, VBAT = 4.0V 4.171 4.3 4.43 V
VDPM_VBAT_ACC Input voltage regulation accuracy tracking VBAT –3% 3%
IINDPM USB input current regulation limit VVBUS = 5 V, current pulled from SW, IINDPM (REG[4:0] = 00100) = 500 mA, –40 ≤ TJ ≤ 85°C 450 500 mA
VVBUS = 5 V, current pulled from SW, IINDPM (REG[4:0] = 01000) = 900 mA, –40 ≤ TJ ≤ 85°C 750 900 mA
VVBUS = 5 V, current pulled from SW, IINDPM (REG[4:0] = 01110) = 1.5 A, –40 ≤ TJ ≤ 85°C 1.3 1.5 A
IIN_START Input current limit during system start-up sequence 200 mA
BAT PIN OVERVOLTAGE PROTECTION
VBATOVP_RISE Battery overvoltage threshold VBAT rising, as percentage of VBAT_REG 103 104 105 %
VBATOVP_FALL Battery overvoltage threshold VBAT falling, as percentage of VBAT_REG 101 102 103 %
THERMAL REGULATION AND THERMAL SHUTDOWN
TJUNCTION_REG Junction temperature regulation threshold Temperature Increasing, TREG (REG05[1] = 1) = 110℃ 110 °C
TJUNCTION_REG Junction temperature regulation threshold Temperature Increasing, TREG (REG05[1] = 0) = 90℃ 90 °C
TSHUT Thermal shutdown rising temperature Temperature Increasing 160 °C
TSHUT_HYST Thermal shutdown hysteresis 30 °C
JEITA Thermistor Comparator (BUCK MODE)
VT1 T1 (0°C) threshold, charge suspended T1 below this temperature. Charger suspends charge. As Percentage to VREGN 72.4% 73.3% 74.2%
VT1 Falling As Percentage to VREGN 69% 71.5% 74%
VT2 T2 (10°C) threshold, charge back to ICHG/2 and 4.2 V below this temperature As percentage of VREGN 67.2% 68% 69%
VT2 Falling As Percentage to VREGN 66% 66.8% 67.7%
VT3 T3 (45°C) threshold, charge back to ICHG and 4.05V above this temperature. Charger suspends charge. As Percentage to VREGN 43.8% 44.7% 45.8%
VT3 Falling As Percentage to VREGN 45.1% 45.7% 46.2%
VT5 T5 (60°C) threshold, charge suspended above this temperature. As Percentage to VREGN 33.7% 34.2% 35.1%
VT5 Falling As Percentage to VREGN 34.5% 35.3% 36.2%
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
VBCOLD Cold temperature threshold, TS pin voltage rising threshold As Percentage to VREGN  (Approx. -20°C w/ 103AT), TJ = –20°C - 125°C 79.5% 80% 80.5%
VBCOLD Falling TJ = –20°C - 125°C 78.5% 79% 79.5%
VBHOT Hot temperature threshold, TS pin voltage falling threshold As Percentage to VREGN (Approx. 60°C w/ 103AT), TJ = –20°C - 125°C 30.2% 31.2% 32.2%
VBHOT Rising TJ = –20°C - 125°C 33.8% 34.4% 34.9%
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
IHSFET_OCP HSFET cycle-by-cycle over-current threshold 5.2 8.0 A
IBATFET_OCP System over load threshold 6.0 A
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VLSFET_UCP LSFET under-current falling threshold From sync mode to non-sync mode 160 mA
PWM
fSW PWM switching frequency Oscillator frequency, buck mode 1320 1500 1680 kHz
Oscillator frequency, boost mode 1150 1412 1660 kHz
DMAX Maximum PWM duty cycle 97%
BOOST MODE OPERATION
VOTG_REG Boost mode regulation voltage VBAT = 3.8 V, I(PMID) = 0 A, BOOSTV[1:0] = '10' = 5.15 V 4.972 5.126 5.280 V
VOTG_REG_ACC Boost mode regulation voltage accuracy VBAT = 3.8 V, I(PMID) = 0 A, BOOSTV[1:0] = '10' = 5.15 V -3 3 %
VBATLOWV_OTG Battery voltage exiting boost mode VBAT falling, MIN_VBAT_SEL (REG01[0]) = 0 2.6 2.8 2.9 V
VBAT rising, MIN_VBAT_SEL (REG01[0]) = 0 2.9 3.0 3.15 V
VBAT falling, MIN_VBAT_SEL (REG01[0]) = 1 2.4 2.5 2.6 V
VBAT rising, MIN_VBAT_SEL (REG01[0]) = 1 2.7 2.8 2.9 V
IOTG OTG mode output current BOOST_LIM (REG02[7]) = 1 1.2 1.4 1.6 A
IOTG_OCP_ACC Boost mode RBFET over-current protection accuracy BOOST_LIM = 0.5 A (REG02[7] = 0) 0.5 0.722 A
VOTG_OVP OTG overvoltage threshold Rising threshold 5.55 5.8 6.15 V
IOTG_HSZCP HSFET under current falling threshold 100 mA
REGN LDO
VREGN REGN LDO output voltage VVBUS = 9V, IREGN = 40mA 5.6 6 V
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.6 4.7 V
LOGIC I/O PIN CHARACTERISTICS ( CE, PSEL, SCL, SDA,, INT)
VILO Input low threshold CE 0.4 V
VIH Input high threshold CE 1.3 V
IBIAS High-level leakage current CE Pull up rail 1.8 V 1 µA
VILO Input low threshold PSEL 0.4 V
VIH Input high threshold PSEL 1.3 V
IBIAS High-level leakage current PSEL Pull up rail 1.8V 1 µA
LOGIC I/O PIN CHARACTERISTICS ( PG, STAT)
VOL Low-level output voltage 0.4 V