SLUSEC9B October   2020  – July 2024 BQ25618E , BQ25619E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up From Battery Without Input Source
      3. 8.3.3 Power Up From Input Source
        1. 8.3.3.1 Power Up REGN LDO
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 8.3.3.3.1 PSEL Pins Sets Input Current Limit
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Power Up Converter in Buck Mode
        6. 8.3.3.6 HIZ Mode with Adapter Present
      4. 8.3.4 Power Path Management
        1. 8.3.4.1 Narrow Voltage DC (NVDC) Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 Supplement Mode
      5. 8.3.5 Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 JEITA Guideline Compliance During Charging Mode
        5. 8.3.5.5 Charging Safety Timer
      6. 8.3.6 Ship Mode and QON Pin
        1. 8.3.6.1 BATFET Disable (Enter Ship Mode)
        2. 8.3.6.2 BATFET Enable (Exit Ship Mode)
        3. 8.3.6.3 BATFET Full System Reset
      7. 8.3.7 Status Outputs ( STAT, INT , PG )
        1. 8.3.7.1 Power Good Indicator (PG_STAT Bit; BQ25619E only)
        2. 8.3.7.2 Charging Status Indicator (STAT)
        3. 8.3.7.3 Interrupt to Host ( INT)
      8. 8.3.8 Protections
        1. 8.3.8.1 Voltage and Current Monitoring in Buck Mode
          1. 8.3.8.1.1 Input Overvoltage Protection (ACOV)
          2. 8.3.8.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.8.2 Thermal Regulation and Thermal Shutdown
          1. 8.3.8.2.1 Thermal Protection in Buck Mode
        3. 8.3.8.3 Battery Protection
          1. 8.3.8.3.1 Battery Overvoltage Protection (BATOVP)
          2. 8.3.8.3.2 Battery Overdischarge Protection
          3. 8.3.8.3.3 System Overcurrent Protection
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Slave Address and Data Direction Bit
        6. 8.3.9.6 Single Read and Write
        7. 8.3.9.7 Multi-Read and Multi-Write
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor and Resistor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

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発注情報

8.5 Register Maps

I2C Slave Address: 6AH

Default I2C Slave Address: 0x6A (1101 010B + R/ W)

Table 8-5 I2C Registers
Address Access Type Acronym Register Name Section
00h R/W REG00 Input Current Limit Go
01h R/W REG01 Charger Control 0 Go
02h R/W REG02 Charge Current Limit Go
03h R/W REG03 Precharge and Termination Current Limit Go
04h R/W REG04 Battery Voltage Limit Go
05h R/W REG05 Charger Control 1 Go
06h R/W REG06 Charger Control 2 Go
07h R/W REG07 Charger Control 3 Go
08h R REG08 Charger Status 0 Go
09h R REG09 Charger Status 1 Go
0Ah R REG0A Charger Status 2 Go
0Bh R REG0B Part Information Go
0Ch R/W REG0C Charger Control 4 Go

Complex bit access types are encoded to fit into small table cells. Table 8-6 shows the codes that are used for access types in this section.

Table 8-6 I2C Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset Value
-n Value after reset
-X Undefined value

8.5.1 Input Current Limit Register (Address = 00h) [reset = 17h]

Figure 8-15 REG00 Register
7 6 5 4 3 2 1 0
0 0 0 1 0 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-7 REG00 Field Descriptions
Bit Field POR Type Reset Description
7 EN_HIZ 0 R/W by REG_RST
by Watchdog		 HIZ mode enable in Buck Mode.
0 – Disable (default)
1 – Enable
6 TS_IGNORE 0 R/W by REG_RST When charger does not monitor the NTC, host sets this bit to 1 to ignore the TS pin condition during charging.
0 – Include TS pin into charge enable conditions. (default)
1 – Ignore TS pin. Always consider TS is good to allow charging. NTC_FAULT bits are 000 to report normal status.
5 BATSNS_DIS 0 R/W by REG_RST This bit describes BATSNS pin detection status.
0 – BATSNS detected, charge voltage is regulated through BATSNS pin (default)
1 – BATSNS not detected, charge voltage is regulated through BAT pin and not BATSNS pin.
When battery voltage rises above VBAT_DPLZ, host can set BATSNS_DIS = 0 to initiate BATSNS detection
4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input current limit setting (maximum limit, not typical)
Offset: 100 mA
Range: 100 mA (000000) – 3.2 A (11111)
Default: 2400 mA (10111)
IINDPM bits are changed automatically after Section 8.3.3.3 is completed
PSEL HIGH = 500 mA
PSEL LOW = 2.4 A
Host can reprogram IINDPM register bits after input source detection is completed.
3 IINDPM[3] 0 R/W by REG_RST 800 mA
2 IINDPM[2] 1 R/W by REG_RST 400 mA
1 IINDPM[1] 1 R/W by REG_RST 200 mA
0 IINDPM[0] 1 R/W by REG_RST 100 mA
LEGEND: R/W = Read/Write; R = Read only

8.5.2 Charger Control 0 Register (Address = 01h) [reset = 1Ah]

Figure 8-16 REG01 Register
7 6 5 4 3 2 1 0
0 0 0 1 1 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8 REG01 Field Descriptions
Bit Field POR Type Reset Description
7 PFM_DIS 0 R/W by REG_RST PFM disable in buck mode.
0 – PFM enable (default)
1 – PFM disable
6 WD_RST 0 R/W by REG_RST
by Watchdog		 I2C Watchdog timer reset. Back to 0 after watchdog timer reset
0 – Normal (default)
1 – Reset
5 Reserved 0 R/W
4 CHG_CONFIG 1 R/W by REG_RST
by Watchdog		 Battery charging buck mode enable. Charging is enabled when CE pin is pulled low, CHG_CONFIG bit is 1 and charge current is not zero.
0 – Charge Disable
1 – Charge Enable (default)
3 SYS_MIN[2] 1 R/W by REG_RST System minimum voltage setting.
000 – 2.6 V
001 – 2.8 V
010 – 3 V
011 – 3.2 V
100 – 3.4 V
101 – 3.5 V (default)
110 – 3.6 V
111 – 3.7 V
2 SYS_MIN[1] 0 R/W by REG_RST
1 SYS_MIN[0] 1 R/W by REG_RST
0 Reserved 0 R/W
LEGEND: R/W = Read/Write; R = Read only

8.5.3 Charge Current Limit Register (Address = 02h) [reset = 91h]

Figure 8-17 REG02 Register
7 6 5 4 3 2 1 0
1 0 0 1 0 0 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-9 REG02 Field Descriptions
Bit Field POR Type Reset Description
7 Reserved 1 R/W
6 Q1_FULLON 0 R/W by REG_RST In buck mode, charger will fully turn on Q1 RBFET according to this bit setting when IINDPM is below 700 mA. When IINDPM is over 700 mA, Q1 is always fully on.
0 – Partially turn on Q1 for better regulation accuracy when IINDPM is below 700 mA. (default)
1 – Fully turn on Q1 for better efficiency when IINDPM is below 700 mA.
5 ICHG[5] 0 R/W by REG_RST
by Watchdog		 640 mA Fast charge current setting
Default: 340 mA (010001)
Range: 0 mA (0000001) – 1180 mA (111011), 20 mA/step
111100: 1290 mA
111101: 1360 mA
111110: 1430 mA
111111: 1500 mA
ICHG 0 mA disables charge.
4 ICHG[4] 1 R/W by REG_RST
by Watchdog		 320 mA
3 ICHG[3] 0 R/W by REG_RST
by Watchdog		 160 mA
2 ICHG[2] 0 R/W by REG_RST
by Watchdog		 80 mA
1 ICHG[1] 0 R/W by REG_RST
by Watchdog		 40 mA
0 ICHG[0] 1 R/W by REG_RST
by Watchdog		 20 mA
LEGEND: R/W = Read/Write; R = Read only

8.5.4 Precharge and Termination Current Limit Register (Address = 03h) [reset = 12h]

Figure 8-18 REG03 Register
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-10 REG03 Field Descriptions
Bit Field POR Type Reset Description
7 IPRECHG[3] 0 R/W by REG_RST
by Watchdog		 160 mA Precharge current setting
Default: 40 mA (0001)
Range: 20 mA (0000) – 260 mA (1100)
Offset: 20 mA
Note: IPRECHG > 260 mA is clamped to 260 mA (1100)
6 IPRECHG[2] 0 R/W by REG_RST
by Watchdog		 80 mA
5 IPRECHG[1] 0 R/W by REG_RST
by Watchdog		 40 mA
4 IPRECHG[0] 1 R/W by REG_RST
by Watchdog		 20 mA
3 ITERM[3] 0 R/W by REG_RST
by Watchdog		 160 mA Termination current setting
Default: 60 mA (0010)
Range: 20 mA – 260 mA (1100)
Offset: 20 mA
Note: ITERM > 260 mA is clamped to 260 mA (1100)
2 ITERM[2] 0 R/W by REG_RST
by Watchdog		 80 mA
1 ITERM[1] 1 R/W by REG_RST
by Watchdog		 40 mA
0 ITERM[0] 0 R/W by REG_RST
by Watchdog		 20 mA
LEGEND: R/W = Read/Write; R = Read only

8.5.5 Battery Voltage Limit Register (Address = 04h) [reset = 40h]

Figure 8-19 REG04 Register
7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11 REG04 Field Descriptions
Bit Field POR Type Reset Description
7 VBATREG[4] 0 R/W by REG_RST
by Watchdog		 Battery voltage setting, also called VREG.
Default: 4.200 V (01000)
00000 – 3.504 V
00001 – 3.600 V
00010 – 3.696 V
00011 – 3.800 V
00100 – 3.904 V
00101 – 4.000 V
00110 – 4.100 V
00111 – 4.150 V
01000 – 4.200 V
01001 – 11111 – 4.300 V - 4.520 V, 10 mV/step
01110 4.350 V, 10011 4.400 V, 11000 4.450 V, 11101 4.500 V
6 VBATREG[3] 1 R/W by REG_RST
by Watchdog
5 VBATREG[2] 0 R/W by REG_RST
by Watchdog
4 VBATREG[1] 0 R/W by REG_RST
by Watchdog
3 VBATREG[0] 0 R/W by REG_RST
by Watchdog
2 TOPOFF_TIMER[1] 0 R/W by REG_RST
by Watchdog		 Top-off timer setting.
00 – Disabled (Default)
01 – 15 minutes
10 – 30 minutes
11 – 45 minutes
1 TOPOFF_TIMER[0] 0 R/W by REG_RST
by Watchdog
0 VRECHG 0 R/W by REG_RST
by Watchdog		 Battery recharge threshold setting.
0 – 120 mV (default)
1 – 210 mV
LEGEND: R/W = Read/Write; R = Read only

8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Eh]

Figure 8-20 REG05 Register
7 6 5 4 3 2 1 0
1 0 0 1 1 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12 REG05 Field Descriptions
Bit Field POR Type Reset Description
7 EN_TERM 1 R/W by REG_RST
by Watchdog		 Battery charging termination enable.
0 – Disable
1 – Enable (default)
6 Reserved 0 R/W by REG_RST
by Watchdog		 Reserved
5 WATCHDOG[1] 0 R/W by REG_RST
by Watchdog		 Watchdog timer setting.
00 – Disable timer
01 – 40 s (default)
10 – 80 s
11 – 160 s
4 WATCHDOG[0] 1 R/W by REG_RST
by Watchdog
3 EN_TIMER 1 R/W by REG_RST
by Watchdog		 Battery charging safety timer enable, including both fast charge and precharge timers. Precharge timer is 2 hours. Fast charge timer is set by REG05[2]
0 – Disable
1 – Enable timer (default)
2 CHG_TIMER 1 R/W by REG_RST
by Watchdog		 Battery fast charging safety timer setting.
0 – 20 hrs
1 – 10 hrs (default)
1 TREG 1 R/W by REG_RST
by Watchdog		 Thermal Regulation Threshold:
0 – 90°C
1 – 110°C (default)
0 JEITA_VSET (45C-60C) 0 R/W by REG_RST
by Watchdog		 Battery voltage setting during JEITA warm (T3 – T5, typically 45C – 60C)
0 – Set Charge Voltage to 4.1 V (max) (default)
1 – Set Charge Voltage to VREG
LEGEND: R/W = Read/Write; R = Read only

8.5.7 Charger Control 2 Register (Address = 06h) [reset = E6h]

Figure 8-21 REG06 Register
7 6 5 4 3 2 1 0
1 1 1 0 0 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-13 REG06 Field Descriptions
Bit Field POR Type Reset Description
7 OVP[1] 1 R/W by REG_RST VACOV threshold during Buck Mode.
00 – 5.85 V
01 – 6.4 V (5-V input)
10 – 11 V (9-V input)
11 – 14.2 V (12-V input) (default)
6 OVP[0] 1 R/W by REG_RST
5 Reserved 1 R/W
4 Reserved 0 R/W
3 VINDPM[3] 0 R/W by REG_RST 800 mV VINDPM threshold setting
Default: 4.5 V (0110)
Range: 3.9 V (0000) – 5.4 V (1111)
Offset: 3.9 V
2 VINDPM[2] 1 R/W by REG_RST 400 mV
1 VINDPM[1] 1 R/W by REG_RST 200 mV
0 VINDPM[0] 0 R/W by REG_RST 100 mV
LEGEND: R/W = Read/Write; R = Read only

8.5.8 Charger Control 3 Register (Address = 07h) [reset = 4Ch]

Figure 8-22 REG07 Register
7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14 REG07 Field Descriptions
Bit Field POR Type Reset Description
7 IINDET_EN 0 R/W by REG_RST
by Watchdog		 Force input source type detection. After the detection is complete, this bit returns to 0.
0 – Not in input current limit detection. (default)
1 – Force input current limit detection when adapter is present.
6 TMR2X_EN 1 R/W by REG_RST
by Watchdog		 Safety timer is slowed by 2X during input DPM, JEITA cool/warm or thermal regulation.
0 – Disable. Safety timer duration is set by REG05[2].
1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA cool/warm (except ICHG=100%), or thermal regulation. (default)
5 BATFET_DIS 0 R/W by REG_RST BATFET Q4 ON/OFF control. Set this bit to 1 to enter Ship Mode. To reset the device with adapter present, the host shall set BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.
0 – Turn on Q4. (default)
1 – Turn off Q4 after tBATFET_DLY delay time (REG07[3])
4 BATFET_RST_WVBUS 0 R/W by REG_RST Start BATFET full system reset with or without adapter present.
0 – Start BATFET full system reset after adapter is removed from VBUS. (default)
1 – Start BATFET full system reset when adapter is present on VBUS.
3 BATFET_DLY 1 R/W by REG_RST Delay from BATFET_DIS (REG07[5]) set to 1 to BATFET turn off during Ship Mode.
0 – Turn off BATFET immediately when BATFET_DIS bit is set.
1 – Turn off BATFET after tBATFET_DLY (typ 10 s) when BATFET_DIS bit is set. (default)
2 BATFET_RST_EN 1 R/W by REG_RST
by Watchdog		 Enable BATFET full system reset. The time to start of BATFET full system reset is based on the setting of BATFET_RST_WVBUS bit.
0 – Disable BATFET reset function
1 – Enable BATFET reset function when REG07[5] is also 1. (default)
1 VINDPM_BAT_TRACK[1] 0 R/W by REG_RST Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VINDPM_BAT_TRACK.
00 – Disable function (VINDPM set by register) (default)
01 – VBAT + 200 mV
10 – VBAT + 250 mV
11 – VBAT + 300 mV
0 VINDPM_BAT_TRACK[0] 0 R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only

8.5.9 Charger Status 0 Register (Address = 08h)

Figure 8-23 REG08
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-15 REG08 Field Descriptions
Bit Field POR Type Reset Description
7 VBUS_STAT[2] x R NA VBUS Status register
000 – No input
001 – USB Host SDP (500 mA) → PSEL pin HIGH
011 – Adapter 2.4 A → PSEL pin LOW
Software current limit is reported in IINDPM register
6 VBUS_STAT[1] x R NA
5 VBUS_STAT[0] x R NA
4 CHRG_STAT[1] x R NA Charging status:
00 – Not Charging
01 – Precharge or trickle charge (< VBATLOWV)
10 – Fast Charging
11 – Charge Termination
3 CHRG_STAT[0] x R NA
2 PG_STAT x R NA Power Good status (BQ25619E only):
0 – Power Not Good
1 – Power Good
1 THERM_STAT x R NA 0 – Not in thermal regulation
1 – In thermal regulation
0 VSYS_STAT x R NA 0 – Not in SYS_MIN regulation (VBAT > VSYS_MIN)
1 – In SYS_MIN regulation (VBAT < VSYS_MIN)
LEGEND: R/W = Read/Write; R = Read only

8.5.10 Charger Status 1 Register (Address = 09h)

Figure 8-24 REG09 Register
7 6 5 4 3 2 1 0
1 x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-16 REG09 Field Descriptions
Bit Field POR Type Reset Description
7 WATCHDOG_FAULT 1 R NA 0 – Normal, device is in Host Mode,
1 – Watchdog timer expiration, device is in Default Mode.
6 Reserved x R NA
5 CHRG_FAULT[1] x R NA 00 – Normal
01 – Input fault
10 – Thermal shutdown
11 – Charge safety timer expiration
4 CHRG_FAULT[0] x R NA
3 BAT_FAULT x R NA 0 – Normal,
1 – Battery overvoltage.
2 NTC_FAULT[2] x R NA TS fault in Buck Mode
000 – Normal
010 – Warm
011 – Cool
101 – Cold
110 – Hot
1 NTC_FAULT[1] x R NA
0 NTC_FAULT[0] x R NA
LEGEND: R/W = Read/Write; R = Read only

8.5.11 Charger Status 2 Register (Address = 0Ah)

Figure 8-25 REG0A Register
7 6 5 4 3 2 1 0
x x x x x x 0 0
R R R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-17 REG0A Field Descriptions
Bit Field POR Type Reset Description
7 VBUS_GD x R NA 0 – VBUS does not pass poor source detection
1 – VBUS passes poor source detection
6 VINDPM_STAT x R NA 0 – Not in VINDPM
1 – In VINDPM
5 IINDPM_STAT x R NA 0 – Not in IINDPM
1 – In IINDPM
4 Reserved x R NA
3 TOPOFF_ACTIVE x R NA 0 – Top off timer not counting.
1 – Top off timer counting
2 ACOV_STAT x R NA 0 – Not in ACOV
1 – In ACOV
1 VINDPM_INT_ MASK 0 R/W by REG_RST Allow or block INT pulse assertion to host during VINDPM.
0 – INT is asserted to host during VINDPM (default)
1 – No INT pulse asserted to host during VINDPM
0 IINDPM_INT_ MASK 0 R/W by REG_RST Allow or block INT pulse assertion to host during IINDPM
0 – INT is asserted to host during IINDPM (default)
1 – No INT pulse asserted to host during IINDPM
LEGEND: R/W = Read/Write; R = Read only

8.5.12 Part Information Register (Address = 0Bh)

Figure 8-26 REG0B Register
7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
R/W R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18 REG0B Field Descriptions
Bit Field POR Type Reset Description
7 REG_RST 0 R/W NA Register reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer. This bit returns to 0 after register reset is completed.
6 PN[3] 1 R NA DEVICE_ID
5 PN[2] 0 R NA
4 PN[1] 0 R NA
3 PN[0] 0 R NA
2
Reserved		 1 R NA Reserved
1
Reserved		 0 R NA Reserved
0
Reserved		 0 R NA
LEGEND: R/W = Read/Write; R = Read only

8.5.13 Charger Control 4 Register (Address = 0Ch) [reset = 75h]

Figure 8-27 REG0C
7 6 5 4 3 2 1 0
0 1 1 1 0 1 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19 REG0C Field Descriptions
Bit Field POR Type Reset Description
7 JEITA_COOL_ISET [1] 0 R/W by REG_RST
by Watchdog		 Fast charge current setting during cool temperature range (T1 - T2), as percentage of ICHG in REG02[5:0].
00 – No Charge
01 – 20% of ICHG (default)
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X)
6 JEITA_COOL_ISET [0] 1 R/W by REG_RST
by Watchdog
5 JEITA_WARM_ISET [1] 1 R/W by REG_RST
by Watchdog		 Fast charge current setting during warm temperature range (T3 – T5), as percentage of ICHG in REG02[5:0].
00 – No Charge
01 – 20% of ICHG
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X) (default)
4 JEITA_WARM_ISET [0] 1 R/W by REG_RST
by Watchdog
3 JEITA_VT2 [1] 0 R/W by REG_RST
by Watchdog		 00 – VT2% = 70.75% (5.5°C)
01 – VT2% = 68.25% (10°C) (default)
10 – VT2% = 65.25% (15°C)
11 – VT2% = 62.25% (20°C)
2 JEITA_VT2 [0] 1 R/W by REG_RST
by Watchdog
1 JEITA_VT3 [1] 0 R/W by REG_RST
by Watchdog		 00 – VT3% = 48.25% (40°C)
01 – VT3% = 44.75% (44.5°C) (default)
10 – VT3% = 40.75% (50.5°C)
11 – VT3% = 37.75% (54.5°C)
0 JEITA_VT3 [0] 1 R/W by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only