SLUSEC9B October   2020  – July 2024 BQ25618E , BQ25619E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up From Battery Without Input Source
      3. 8.3.3 Power Up From Input Source
        1. 8.3.3.1 Power Up REGN LDO
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 8.3.3.3.1 PSEL Pins Sets Input Current Limit
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Power Up Converter in Buck Mode
        6. 8.3.3.6 HIZ Mode with Adapter Present
      4. 8.3.4 Power Path Management
        1. 8.3.4.1 Narrow Voltage DC (NVDC) Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 Supplement Mode
      5. 8.3.5 Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 JEITA Guideline Compliance During Charging Mode
        5. 8.3.5.5 Charging Safety Timer
      6. 8.3.6 Ship Mode and QON Pin
        1. 8.3.6.1 BATFET Disable (Enter Ship Mode)
        2. 8.3.6.2 BATFET Enable (Exit Ship Mode)
        3. 8.3.6.3 BATFET Full System Reset
      7. 8.3.7 Status Outputs ( STAT, INT , PG )
        1. 8.3.7.1 Power Good Indicator (PG_STAT Bit; BQ25619E only)
        2. 8.3.7.2 Charging Status Indicator (STAT)
        3. 8.3.7.3 Interrupt to Host ( INT)
      8. 8.3.8 Protections
        1. 8.3.8.1 Voltage and Current Monitoring in Buck Mode
          1. 8.3.8.1.1 Input Overvoltage Protection (ACOV)
          2. 8.3.8.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.8.2 Thermal Regulation and Thermal Shutdown
          1. 8.3.8.2.1 Thermal Protection in Buck Mode
        3. 8.3.8.3 Battery Protection
          1. 8.3.8.3.1 Battery Overvoltage Protection (BATOVP)
          2. 8.3.8.3.2 Battery Overdischarge Protection
          3. 8.3.8.3.3 System Overcurrent Protection
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Slave Address and Data Direction Bit
        6. 8.3.9.6 Single Read and Write
        7. 8.3.9.7 Multi-Read and Multi-Write
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor and Resistor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT  Quiescent battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5V, VBUS floating, SCL, SDA = 0V or 1.8V, TJ < 85 °C, BATFET enabled  9.5 15 µA
ISHIP_BAT  Shipmode battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5V, VBUS floating, SCL, SDA = 0V or 1.8V, TJ < 85 °C, BATFET disabled 7 9.5 µA
IVBUS Input current (VBUS) in buck mode when converter is switching VBUS=5V, charge disabled, converter switching, ISYS = 0A 2.3 mA
IHIZ_VBUS  Quiescent input current in HIZ VAC/VBUS = 5V, HIZ mode, no battery 37 50 µA
VAC/VBUS = 12V, HIZ mode, no battery 68 90 µA
VBUS / VBAT SUPPLY
VVBUS_OP VBUS operating range 4 13.5 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.3 3.7 V
VVBUS_UVLO VBUS falling to turnoff I2C, no battery VBUS falling 3 3.3 V
VVBUS_PRESENT VBUS to enable REGN VBUS rising 3.65 3.9 V
VVBUS_PRESENTZ VBUS to disable REGN VBUS falling 3.15 3.4 V
VSLEEP Enter Sleep mode threshold VBUS falling, VBUS - VBAT, VBAT = 4V 15 60 110 mV
VSLEEPZ Exit Sleep mode threshold VBUS rising, VBUS - VBAT, VBAT = 4V 115 220 340 mV
VACOV  VAC overvoltage rising threshold to turn off switching VAC rising, OVP[1:0]=00 5.45 5.85 6.07 V
VAC rising, OVP[1:0]=01 6.1 6.4 6.75 V
VAC rising, OVP[1:0]=10 10.45 11 11.55 V
VAC rising, OVP[1:0]=11 (default) 13.5 14.2 14.85 V
VAC overvoltage falling threshold to resume switching VAC falling, OVP[1:0]=00 5.2 5.6 5.8 V
VAC falling, OVP[1:0]=01 5.8 6.2 6.45 V
VAC falling, OVP[1:0]=10 10 10.7 11.1 V
VAC falling, OVP[1:0]=11 (default) 13 13.9 14.5 V
VBAT_UVLOZ BAT voltage for active I2C, no VBUS VBAT rising 2.5 V
VBAT_DPLZ BAT depletion rising threshold to turn on BATFET VBAT rising 2.35 2.8 V
VBAT_DPL BAT depletion falling threshold to turn off BATFET VBAT falling 2.18 2.62 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.75 3.9 4.0 V
POWER-PATH MANAGEMENT
VSYS_MIN Typical minimum system regulation voltage VBAT=3.2V < SYS_MIN = 3.5V, ISYS = 0A 3.5 3.65 V
VSYS_OVP System overvoltage threshold VREG = 4.35V, Charge disabled, ISYS = 0A 4.7 V
RON_RBFET Blocking FET on-resistance (BQ25618E) 35 mΩ
RON_RBFET Blocking FET on-resistance (BQ25619E) 45 mΩ
RON_HSFET High-side switching FET on-resistance (BQ25618E) 55 mΩ
RON_HSFET High-side switching FET on-resistance (BQ25619E) 62 mΩ
RON_LSFET Low-side switching FET on-resistance (BQ25618E) 60 mΩ
RON_LSFET Low-side switching FET on-resistance (BQ25619E) 71 mΩ
VBATFET_FWD BATFET forward voltage in supplement mode BAT discharge current 10mA, converter running 30 mV
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3.5 4.52 V
VREG_STEP Typical charge voltage step 4.3V < VREG < 4.52V 10 mV
VREG_ACC Charge voltage accuracy VREG = 4.2V, TJ = –40°C - 85°C 4.179 4.2 4.221 V
VREG = 4.35V, TJ = –40°C - 85°C 4.329 4.35 4.371 V
VREG = 4.45V, TJ = –40°C - 85°C 4.428 4.45 4.472 V
ICHG_RANGE  Typical charge current regulation range 0 1.5 A
ICHG_STEP  Typical charge current regulation step 20 mA
ICHG_ACC  Fast charge current regulation accuracy ICHG = 0.24A, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 0.216 0.24 0.264 A
ICHG = 0.72A, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 0.6768 0.72 0.7632 A
ICHG = 1.50A, VBAT = 3.1V or 3.8V, TJ = –40°C - 85°C 1.41 1.5 1.59 A
IPRECHG_RANGE  Typical pre-charge current range 20 260 mA
IPRECHG_STEP  Typical pre-charge current step 20 mA
IPRECHG_ACC Precharge current accuracy VBAT = 2.6V, IPRECHG = 40mA 28 40 52 mA
VBAT = 2.6V, IPRECHG = 120mA 84 120 156 mA
ITERM_RANGE  Typical termination current range 20 260 mA
ITERM_STEP  Typical termination current step 20 mA
ITERM_ACC  Termination current accuracy ITERM=40mA, ICHG>260mA, VREG=4.35V, TJ = 0°C - 85°C 30 40 50 mA
ITERM=20mA, ICHG<260mA, VREG=4.35V, TJ = 0°C - 85°C  10 20 30 mA
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.13 2.25 2.35 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling 1.85 2 2.15 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ 15 25 30 mA
VBATLOWV Battery LOWV rising threshold to start fast-charge VBAT rising 3 3.12 3.24 V
Battery LOWV falling threshold to stop fast-charge VBAT falling 2.7 2.8 2.9 V
VRECHG  Battery recharge threshold VRECHG=0, VBAT falling (default) 90 120 150 mV
VRECHG=1, VBAT falling 185 210 245 mV
ISYS_LOAD System discharge load current during SYSOVP 30 mA
RON_BATFET Battery FET on-resistance TJ = -40°C - 85°C 19.5 26 mΩ
TJ = -40°C - 125°C 19.5 30 mΩ
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP Battery overvoltage rising threshold VBAT rising, as percentage of VREG 103 104 105 %
Battery overvoltage falling threshold VBAT falling, as percentage of VREG 101 102 103 %
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.9 5.4 V
VINDPM_STEP Typical input voltage regulation step 100 mV
VINDPM_ACC  Typical input voltage regulation accuracy 4.365 4.5 4.635 V
VINDPM_TRACK  VINDPM threshold to track battery voltage VBAT = 4.35V, VINDPM_BAT_TRACK = VBAT+200mV 4.45 4.55 4.74 V
IINDPM_RANGE Typical input current regulation range 0.1 3.2 A
IINDPM_STEP Typical input current regulation step 100 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA (TJ=-40°C - 85°C) 450 465 500 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 900mA (TJ=-40°C-85°C) 750 835 900 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 1500mA (TJ=-40°C-85°C) 1300 1390 1500 mA
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 90°C 90 °C
TREG = 110°C 110 °C
TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 130 °C
CHARGE MODE THERMISTOR COMPARATOR
VT1_RISE% TS pin voltage rising threshold, Charge suspended above this voltage. As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL% TS pin voltage falling threshold. Charge re-enabled to 20% of ICHG and VREG below this
voltage. 		 As Percentage to REGN 71.5 72 72.5 %
VT2_RISE%  TS pin voltage rising threshold, Charge back to 20% of ICHG and VREG above this voltage.  As Percentage to REGN, JEITA_T2=5°C w/ 103AT 70.25 70.75 71.25 %
As Percentage to REGN, JEITA_T2=10°C w/ 103AT 67.75 68.25 68.75 %
As Percentage to REGN, JEITA_T2=15°C w/ 103AT 64.75 65.25 65.75 %
As Percentage to REGN, JEITA_T2=20°C w/ 103AT 61.75 62.25 62.75 %
VT2_FALL% TS pin voltage falling threshold. Charge back to ICHG and VREG below this voltage.  As Percentage to REGN, JEITA_T2=5°C w/ 103AT 68.7 69.2 69.7 %
As Percentage to REGN, JEITA_T2=10°C  w/ 103AT 66.45 66.95 67.45 %
As Percentage to REGN, JEITA_T2=15°C  w/ 103AT 63.7 64.2 64.7 %
As Percentage to REGN, JEITA_T2=20°C  w/ 103AT 60.7 61.2 61.7 %
VT3_FALL% TS pin voltage falling threshold. Charge to ICHG and 4.1V below this voltage.  As Percentage to REGN, JEITA_T3=40°C  w/ 103AT 47.75 48.25 48.75 %
As Percentage to REGN, JEITA_T3=45°C  w/ 103AT 44.25 44.75 45.25 %
As Percentage to REGN, JEITA_T3=50°C  w/ 103AT 40.2 40.7 41.2 %
As Percentage to REGN, JEITA_T3=55°C  w/ 103AT 37.2 37.7 38.2 %
VT3_RISE% TS pin voltage rising threshold. Charge back to ICHG and VREG above this voltage.  As Percentage to REGN, JEITA_T3=40°C w/ 103AT 48.8 49.3 49.8 %
As Percentage to REGN, JEITA_T3=45°C w/ 103AT 45.3 45.8 46.3 %
As Percentage to REGN, JEITA_T3=50°C w/ 103AT 41.3 41.8 42.3 %
As Percentage to REGN, JEITA_T3=55°C w/ 103AT 38.5 39 39.5 %
VT5_FALL% TS pin voltage falling threshold, charge suspended below this voltage.  As Percentage to REGN (60°C w/ 103AT) 33.7 34.2 35.1 %
VT5_RISE% TS pin voltage rising threshold. Charge back to ICHG and 4.1V above this voltage.  As Percentage to REGN 35 35.5 36 %
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.32 1.5 1.68 MHz
DMAX Maximum PWM Duty Cycle 97 %
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.58 4.7 4.8 V
VVBUS = 9V, IREGN = 20mA 5.6 6 6.5 V
IREGN REGN LDO current limit VVBUS = 5V, VREGN = 3.8V 50 mA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL Pull up rail 1.8V 1.3 V
VIL Input low threshold level Pull up rail 1.8V 0.4 V
VOL Output low threshold level Sink current = 5mA 0.4 V
IBIAS High-level leakage current Pull up rail 1.8V 1 µA
VIH_SDA Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SDA Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SDA Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SDA High-level leakage current Pull up rail 1.8V 1 µA
VIH_SCL Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SCL Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SCL Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SCL High-level leakage current Pull up rail 1.8V 1 µA
LOGIC INPUT PIN
VIH Input high threshold level (/CE, PSEL) 1.3 V
VIL  Input low threshold level (/CE, PSEL) 0.4 V
IIN_BIAS  High-level leakage current (/CE, PSEL) Pull up rail 1.8V 1 µA
LOGIC OUTPUT PIN
VOL Output low threshold level (/INT, STAT, /PG) Sink current = 5mA 0.4 V
IOUT_BIAS High-level leakage current (/INT, STAT, /PG) Pull up rail 1.8V 1 µA