JAJSKU7C September   2022  – February 2024 BQ25620 , BQ25622

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25620 Only)
        4. 8.3.3.4 ILIM Pin (BQ25622 Only)
        5. 8.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 8.3.3.6 Converter Power-Up
      4. 8.3.4  Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5  Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 8.3.5.4.4 JEITA Charge Rate Scaling
          5. 8.3.5.4.5 TS_BIAS Pin (BQ25622 Only)
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 Boost OTG Mode
      7. 8.3.7  Integrated 12-Bit ADC for Monitoring
      8. 8.3.8  Status Outputs ( PG, STAT, INT)
        1. 8.3.8.1 PG Pin Power Good Indicator
        2. 8.3.8.2 Interrupts and Status, Flag and Mask Bits
        3. 8.3.8.3 Charging Status Indicator (STAT)
        4. 8.3.8.4 Interrupt to Host ( INT)
      9. 8.3.9  BATFET Control
        1. 8.3.9.1 Shutdown Mode
        2. 8.3.9.2 Ship Mode
        3. 8.3.9.3 System Power Reset
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.10.1.1 Battery Undervoltage Lockout
          2. 8.3.10.1.2 Battery Overcurrent Protection
        2. 8.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.10.2.1 Input Overvoltage
          2. 8.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.10.2.4 System Short
          5. 8.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.10.2.6 Sleep and Poor Source Comparators
        3. 8.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.3.1 Boost Mode Overvoltage Protection
          2. 8.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 8.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 8.3.10.3.4 Boost Mode Battery Undervoltage
          5. 8.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 8.3.10.3.6 Boost Mode SYS Short
        4. 8.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.4.1 Thermal Protection in Buck Mode
          2. 8.3.10.4.2 Thermal Protection in Boost Mode
          3. 8.3.10.4.3 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25620 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20200829-CA0I-VXPC-8XL2-BWJJN9J1G9WQ-low.svg Figure 6-1 BQ25620 Pinout,18-Pin WQFNTop View
GUID-20200829-CA0I-M1H9-LXFS-B4RW1HKG97X7-low.svg Figure 6-2 BQ25622 Pinout,18-Pin WQFNTop View
Table 6-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
BQ25622 BQ25620
BTST 1 P High Side Switching MOSFET Gate Driver Power Supply – Connect a 10 V or higher rating, 47-nF ceramic capacitor between SW and BTST as the bootstrap capacitor for driving high side switching MOSFET (Q2).
REGN 2 P The Charger Internal Linear Regulator Output – Internally, REGN is connected to the anode of the boost-strap diode. Connect a 10 V or higher rating, 4.7-μF ceramic capacitor from REGN to power ground, The capacitor should be placed close to the IC. The REGN LDO output is used for the internal MOSFETs gate driving voltage and for biasing the external TS pin thermistor in BQ25620.
PG 3 DO Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW indicates an input source of VVBUS_UVLO < VBUS < VVBUS_OVP. Failing poor source detection or triggering the sleep comparator ( VBUS < VBAT + VSLEEP ) also causes PG to transition HIGH.
ILIM D- 4 AIO Input Current Limit Setting Input Pin – ILIM pin sets the input current limit as IINREG = KILIM / RILIM, where RILIM is connected from ILIM pin to GND. The input current is limited to the lower of the two values set by ILIM pin and IINDPM register bits. The ILIM pin can also be used to monitor input current. The input current is proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8). The ILIM pin function is disabled when EN_EXTILIM bit is set to 0.
Negative Line of the USB Data Line Pair – D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2.
TS_BIAS D+ 5 P Bias for the TS Resistor Voltage Divider – Provides the bias voltage for the TS resistor voltage divider.
AIO Positive Line of the USB Data Line Pair – D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2.
TS 6 AI Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from TS pin bias reference (REGN in BQ25620, TS_BIAS in BQ25622) to TS, then to GND. Charge suspends when TS pin voltage is out of range. Recommend a 103AT-2 10-kΩ thermistor.
QON 7 DI BATFET Enable or System Power Reset Control Input – If the charger is in ship mode, a logic low on this pin with tSM_EXIT duration forces the device to exit ship mode. If the charger is not in ship mode, a logic low on this pin with tQON_RST initiates a full system power reset if either VVBUS < VVBUS_UVLO or BATFET_CTRL_WVBUS = 1. QON has no effect during shutdown mode. The pin contains an internal pull-up to maintain default high logic.
BAT 8 P The Battery Charging Power Connection – Connect to the positive terminal of the battery pack. The internal BATFET is connected between SYS and BAT.
SYS 9 P The Charger Output Voltage to System –The Buck converter output connection point to the system. The internal BATFET is connected between SYS and BAT.
STAT 10 DO Open Drain Charge Status Output – It indicates various charger operations. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charging in progress. HIGH indicates charging completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz. Setting DIS_STAT = 1 disables the STAT pin function, causing the pin to be pulled HIGH. Leave floating if unused.
INT 11 DO Open Drain Interrupt Output. – Connect to the pull up rail via 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to the host to report the charger device status and faults.
SDA 12 DIO I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
SCL 13 DI I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
CE 14 DI Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
GND 15 P Ground Return
SW 16 P Switching Node Connecting to Output Inductor – Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 47-nF bootstrap capacitor from SW to BTST.
PMID 17 P HSFET Drain Connection – Internally PMID is connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
VBUS 18 P Charger Input Voltage – The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power