JAJSKU7C September 2022 – February 2024 BQ25620 , BQ25622
PRODUCTION DATA
The BQ25620 and BQ25622 provide an integrated 12-bit ADC for the host to monitor various system parameters.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is disabled by default (ADC_EN = 0) to conserve power. The ADC is allowed to operate if either VBUS > VPOORSRC or VBAT > VBAT_LOWV is valid. If ADC_EN is set to ‘1’ before VBUS or VBAT reach their respective valid thresholds, then ADC_EN stays '0'. The host can enable the ADC during HIZ mode by setting ADC_EN = 1.
At battery only condition, if the TS_ADC channel is enabled, the ADC only operates when the battery voltage is higher than 3.2 V (the minimal value to turn on REGN), otherwise, the ADC operates when the battery voltage is higher than VBAT_LOWV.
The ADC_DONE_STAT, ADC_DONE_FLAG bits are set when a conversion is complete in one-shot mode only. During continuous conversion mode, the ADC_DONE_STAT, ADC_DONE_FLAG bits have no meaning and remain at 0. In one-shot mode, the ADC_EN bit is set to 0 at the completion of the conversion, at the same time as the ADC_DONE_FLAG bit is set. In continuous mode, the ADC_EN bit remains at 1 until the user disables the ADC by setting it to 0.