JAJSKU7C September   2022  – February 2024 BQ25620 , BQ25622

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25620 Only)
        4. 8.3.3.4 ILIM Pin (BQ25622 Only)
        5. 8.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 8.3.3.6 Converter Power-Up
      4. 8.3.4  Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5  Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 8.3.5.4.4 JEITA Charge Rate Scaling
          5. 8.3.5.4.5 TS_BIAS Pin (BQ25622 Only)
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 Boost OTG Mode
      7. 8.3.7  Integrated 12-Bit ADC for Monitoring
      8. 8.3.8  Status Outputs ( PG, STAT, INT)
        1. 8.3.8.1 PG Pin Power Good Indicator
        2. 8.3.8.2 Interrupts and Status, Flag and Mask Bits
        3. 8.3.8.3 Charging Status Indicator (STAT)
        4. 8.3.8.4 Interrupt to Host ( INT)
      9. 8.3.9  BATFET Control
        1. 8.3.9.1 Shutdown Mode
        2. 8.3.9.2 Ship Mode
        3. 8.3.9.3 System Power Reset
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.10.1.1 Battery Undervoltage Lockout
          2. 8.3.10.1.2 Battery Overcurrent Protection
        2. 8.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.10.2.1 Input Overvoltage
          2. 8.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.10.2.4 System Short
          5. 8.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.10.2.6 Sleep and Poor Source Comparators
        3. 8.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.3.1 Boost Mode Overvoltage Protection
          2. 8.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 8.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 8.3.10.3.4 Boost Mode Battery Undervoltage
          5. 8.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 8.3.10.3.6 Boost Mode SYS Short
        4. 8.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.4.1 Thermal Protection in Buck Mode
          2. 8.3.10.4.2 Thermal Protection in Boost Mode
          3. 8.3.10.4.3 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25620 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT Quiescent battery current (BAT, SYS, SW) when the charger is in the battery only mode, BATFET is enabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is enabled, I2C enabled, ADC disabled, system is powered by battery. -40 °C < TJ < 60 °C 1.5 3 µA
IQ_BAT_ADC Quiescent battery current (BAT, SYS, SW) when the charger is in the battery only mode, BATFET is enabled, ADC is enabled VBAT = 4V, No VBUS, BATFET is enabled, I2C enabled, ADC enabled, system is powered by battery. -40 °C < TJ < 60 °C 260 µA
IQ_BAT_SD Quiescent battery current (BAT) when the charger is in shutdown mode, BATFET is disabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is disabled, I2C disabled, in shutdown mode, ADC disabled, TJ < 60 °C 0.1 0.2 µA
IQ_BAT_SHIP Quiescent battery current (BAT) when the charger is in ship mode, BATFET is disabled, ADC is disabled VBAT = 4V, No VBUS, BATFET is disabled, I2C disabled, in ship mode, ADC disabled, TJ < 60 °C 0.15 0.5 µA
IQ_VBUS Quiescent input current (VBUS) VBUS = 5V, VBAT = 4V, charge disabled, converter switching, ISYS = 0A, PFM enabled 450 µA
IQ_VBUS_HIZ Quiescent input current (VBUS) in HIZ VBUS = 5V, VBAT = 4V, HIZ mode, ADC disabled 5 20 µA
VBUS = 15V, VBAT = 4V, HIZ mode, ADC disabled 20 35 µA
IQ_OTG Quiescent battery current (BAT, SYS, SW) in boost OTG mode VBAT = 4.2V, VBUS = 5V, OTG mode enabled, converter switching, PFM enabled, IVBUS = 0A, TS float, TS_IGNORE = 1 250 µA
VBUS / VBAT SUPPLY
VVBUS_OP VBUS operating range 3.9 18 V
VVBUS_UVLO VBUS falling to turn off I2C, no battery VBUS falling 3.0 3.15 3.3 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.2 3.35 3.5 V
VVBUS_OVP VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 0 6.1 6.4 6.7 V
VVBUS_OVPZ VBUS overvoltage falling hreshold VBUS rising, VBUS_OVP = 0 5.8 6.0 6.2 V
VVBUS_OVP VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 1 18.2 18.5 18.8 V
VVBUS_OVPZ VBUS overvoltage falling threshold VBUS falling, VBUS_OVP = 1 17.4 17.7 18.0 V
VSLEEP Enter Sleep mode threshold (VBUS - VBAT), VBUS falling 9 45 85 mV
VSLEEPZ Exit Sleep mode threshold (VBUS - VBAT), VBUS rising 115 220 340 mV
VBAT_UVLOZ BAT voltage for active I2C, turn on BATFET, no VBUS VBAT rising 2.3 2.4 2.5 V
VBAT_UVLO BAT voltage to turnoff I2C, turn off BATFET, no VBUS VBAT falling, VBAT_UVLO = 0 2.1 2.2 2.3 V
VBAT falling, VBAT_UVLO = 1 1.7 1.8 1.9 V
VBAT_OTG BAT voltage rising threshold to enable OTG mode VBAT rising, VBAT_OTG_MIN = 0 2.9 3.0 3.1 V
VBAT rising, VBAT_OTG_MIN = 1 2.5 2.6 2.7 V
VBAT_OTGZ BAT voltage falling threshold to disable OTG mode VBAT falling, VBAT_OTG_MIN = 0 2.7 2.8 2.9 V
VBAT falling, VBAT_OTG_MIN = 1 2.3 2.4 2.5 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.6 3.7 3.75 V
IPOORSRC Bad adapter detection current source 10 mA
POWER-PATH MANAGEMENT
VSYS_REG_ACC Typical system voltage regulation ISYS = 0A, VBAT > VSYSMIN, Charge Disabled. Offset above VBAT 50 mV
ISYS = 0A, VBAT < VSYSMIN, Charge Disabled. Offset above VSYSMIN 230 mV
VSYSMIN_RNG VSYSMIN register range 2.56 3.84 V
VSYSMIN_REG_STEP VSYSMIN register step size 80 mV
VSYSMIN_REG_ACC Minimum DC system voltage output ISYS = 0A, VBAT < VSYSMIN = B00h (3.52V), Charge Disabled 3.52 3.75 V
VSYS_SHORT VSYS short voltage falling threshold to enter forced PFM 0.9 V
VSYS_SHORTZ VSYS short voltage rising threshold to exit forced PFM 1.1 V
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3.50 4.80 V
VREG_STEP Typical charge voltage step 10 mV
VREG_ACC Charge voltage accuracy TJ = 25°C –0.3 0.3 %
TJ = –10°C - 85°C –0.4 0.4 %
ICHG_RANGE Typical charge current regulation range 0.08 3.52 A
ICHG_STEP Typical charge current regulation step 80 mA
ICHG_ACC Charge current accuracy VBAT = 3.1V or 3.8V, ICHG = 1760mA, TJ = –10°C - 85°C –5 5 %
VBAT = 3.1V or 3.8V, ICHG = 1040mA, TJ = –10°C - 85°C –5.5 5.5 %
VBAT = 3.1V or 3.8V, ICHG = 320mA, TJ = –10°C - 85°C –5.5 5.5 %
IPRECHG_RANGE Typical pre-charge current range 20 620 mA
IPRECHG_STEP Typical pre-charge current step 20 mA
IPRECHG_ACC Pre-charge current accuracy when VBAT below VSYSMIN setting VBAT = 2.5V, IPRECHG = 500mA, TJ = –10°C - 85°C –12 12 %
VBAT = 2.5V, IPRECHG = 200mA, TJ = –10°C - 85°C –12 12 %
VBAT = 2.5V, IPRECHG = 100mA, TJ = –10°C - 85°C –15 15 %
ITERM_RANGE Typical termination current range 10 620 mA
ITERM_STEP Typical termination current step 10 mA
ITERM_ACC Termination current accuracy ITERM = 20mA, TJ = –10°C - 85°C –60 60 %
ITERM = 100mA, TJ = –10°C - 85°C –15 15 %
ITERM = 300mA, TJ = –10°C - 85°C –13 13 %
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.25 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling, VBAT_UVLO=0 2.05 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling, VBAT_UVLO=1 1.85 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ, ITRICKLE = 0 15 25 35 mA
VBAT < VBAT_SHORTZ, ITRICKLE = 1  62 82 102 mA
VBAT_LOWVZ Battery voltage rising threshold Transition from pre-charge to fast charge 2.9 3.0 3.1 V
VBAT_LOWV Battery voltage falling threshold Transition from fast charge to pre-charge 2.7 2.8 2.9 V
VRECHG Battery recharge threshold below VREG VBAT falling, VRECHG = 0 100 mV
VBAT falling, VRECHG = 1 200 mV
IPMID_LOAD PMID discharge load current 20 30 mA
IBAT_LOAD Battery discharge load current 20 30 mA
ISYS_LOAD System discharge load current 20 30 mA
BATFET
RBATFET MOSFET on resistance from SYS to BAT 15 25 mΩ
BATTERY PROTECTIONS
VBAT_OVP Battery overvoltage rising threshold As percentage of VREG 103 104 105 %
VBAT_OVPZ Battery overvoltage falling threshold As percentage of VREG 101 102 103 %
IBATFET_OCP BATFET over-current rising threshold 6 A
IBAT_PK Battery discharging peak current rising threshold IBAT_PK = 00 1.5 A
IBAT_PK = 01 3 A
IBAT_PK = 10 6 A
IBAT_PK = 11 12 A
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.8 16.8 V
VINDPM_STEP Typical input voltage regulation step 40 mV
VINDPM_ACC Input voltage regulation accuracy VINDPM=4.6V –4 4 %
VINDPM=8V –3 3 %
VINDPM=16V –2 2 %
VINDPM_BAT_TRACK Battery tracking VINDPM accuracy VBAT = 3.9V, VINDPM_BAT_TRACK=1, VINDPM = 4V 4.15 4.3 4.45 V
IINDPM_RANGE Typical input current regulation range 0.04 3.2 A
IINDPM_STEP Typical input current regulation step 20 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA, VBUS=5V 450 475 500 mA
IINDPM = 900mA, VBUS=5V 810 855 900 mA
IINDPM = 1500mA, VBUS=5V 1350 1425 1500 mA
KILIM ILIM Pin Scale Factor, IINREG = KILIM / RILIM INREG = 1.6 A 2250 2500 2750 AΩ
D+ / D- DETECTION
VD+D-_0p6V_SRC D+/D- voltage source (600 mV) 1 mA load on D+/D- 400 600 800 mV
ID+D-_LKG Leakage current into D+/D- HiZ mode –1 1 µA
VD+D-_2p8 D+/D- comparator threshold for non-standard adapter 2.55 2.85 V
VD+D-_2p0 D+/D- comparator threshold for non-standard adapter 1.85 2.15 V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 1 120 °C
TREG = 0 60 °C
TSHUT Thermal Shutdown Rising Threshold Temperature Increasing 140 °C
TSHUT_HYS Thermal Shutdown Falling Hysteresis Temperature Decreasing by TSHUT_HYS 30 °C
THERMISTOR COMPARATORS (CHARGE MODE)
VTS_COLD TS pin rising voltage threshold for TH1 comparator to transition from TS_COOL to TS_COLD.  Charge suspended above this voltage. As Percentage to TS pin bias reference (-5°C w/ 103AT), TS_TH1_TH2_TH3 = 100, 101, 110 75.0 75.5 76.0 %
As Percentage to TS pin bias reference (0°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 001, 010, 011, 111 72.8 73.3 73.8 %
VTS_COLDZ TS pin falling voltage threshold for TH1 comparator to transition from TS_COLD to TS_COOL.  TS_COOL charge settings resume below this voltage. As Percentage to TS pin bias reference (-2.5°C w/ 103AT), TS_TH1_TH2_TH3 = 100, 101, 110 73.9 74.4 74.9 %
As Percentage to TS pin bias reference (2.5°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 001, 010, 011, 111 71.7 72.2 72.7 %
VTS_COOL TS pin rising voltage threshold for TH2 comparator to transition from TS_PRECOOL to TS_COOL.  TS_COOL charging settings used above this voltage. As Percentage to TS pin bias reference (5°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 100 70.6 71.1 71.6 %
As Percentage to TS pin bias reference (10°C w/ 103AT), TS_TH1_TH2_TH3 = 001, 101, 110, 111 67.9 68.4 68.9 %
As Percentage to TS pin bias reference (15°C w/ 103AT), TS_TH1_TH2_TH3 = 010 65.0 65.5 66.0 %
As Percentage to TS pin bias reference (20°C w/ 103AT), TS_TH1_TH2_TH3 = 011 61.9 62.4 62.9 %
VTS_COOLZ TS pin falling voltage threshold for TH2 comparator to transition from TS_COOL to TS_PRECOOL.  TS_PRECOOL charging settings resume below this voltage. As Percentage to TS pin bias reference (7.5°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 100 69.3 69.8 70.3 %
As Percentage to TS pin bias reference (12.5°C w/ 103AT), TS_TH1_TH2_TH3 = 001, 101, 110, 111 66.6 67.1 67.6 %
As Percentage to TS pin bias reference (17.5°C w/ 103AT), TS_TH1_TH2_TH3 = 010 63.7 64.2 64.7 %
As Percentage to TS pin bias reference (22.5°C w/ 103AT), TS_TH1_TH2_TH3 = 011 60.6 61.1 61.6 %
VTS_PRECOOL TS pin rising voltage threshold for TH3 comparator to transition from TS_NORMAL to TS_PRECOOL.  TS_PRECOOL charge settings used above this voltage. As Percentage to TS pin bias reference (15°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 001, 100, 101 65.0 65.5 66.0 %
As Percentage to TS pin bias reference (20°C w/ 103AT), TS_TH1_TH2_TH3 = 010, 011, 110, 111 61.9 62.4 62.9 %
VTS_PRECOOLZ TS pin falling voltage threshold for TH3 comparator to transition from TS_PRECOOL to TS_NORMAL.  Normal charging resumes below this voltage. As Percentage to TS pin bias reference (17.5°C w/ 103AT), TS_TH1_TH2_TH3 = 000, 001, 100, 101 63.7 64.2 64.7 %
As Percentage to TS pin bias reference (22.5°C w/ 103AT), TS_TH1_TH2_TH3 = 010, 011, 110, 111 60.6 61.1 61.6 %
VTS_PREWARM TS pin falling voltage threshold for TH4 comparator to transition from TS_NORMAL to TS_PREWARM.  TS_PREWARM charging settings used below this voltage. As Percentage to TS pin bias reference (35°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 001, 010, 100, 101 51.5 52.0 52.5 %
As Percentage to TS pin bias reference (40°C w/ 103AT), TS_TH4_TH5_TH6 = 011, 110, 111 47.9 48.4 48.9 %
VTS_PREWARMZ TS pin rising voltage threshold for TH4 comparator to transition from TS_PREWARM to TS_NORMAL.  Normal charging resumes above this voltage. As Percentage to TS pin bias reference (32.5°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 001, 010, 100, 101 53.3 53.8 54.3 %
As Percentage to TS pin bias reference (37.5°C w/ 103AT), TS_TH4_TH5_TH6 = 011, 110, 111 49.2 49.7 50.2 %

VTS_WARM
 		 TS pin falling voltage threshold for TH5 comparator to transition from TS_PREWARM to TS_WARM.  TS_WARM charging settings used below this voltage. As Percentage to TS pin bias reference (40°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 100 47.9 48.4 48.9 %
As Percentage to TS pin bias reference (45°C w/ 103AT), TS_TH4_TH5_TH6 = 001, 101, 110 44.3 44.8 45.3 %
As Percentage to TS pin bias reference (50°C w/ 103AT), TS_TH4_TH5_TH6 = 010, 111 40.7 41.2 41.7 %
As Percentage to TS pin bias reference (55°C w/ 103AT), TS_TH4_TH5_TH6 = 011 37.2 37.7 38.2 %
VTS_WARMZ TS pin rising voltage threshold for TH5 comparator to transition from TS_WARM to TS_PREWARM.  TS_PREWARM charging settings resume above this voltage. As Percentage to TS pin bias reference (37.5°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 100 49.2 49.7 50.2 %
As Percentage to TS pin bias reference (42.5°C w/ 103AT), TS_TH4_TH5_TH6 = 001, 101, 110 45.6 46.1 46.6 %
As Percentage to TS pin bias reference (47.5°C w/ 103AT), TS_TH4_TH5_TH6 = 010, 111 42.0 42.5 43.0 %
As Percentage to TS pin bias reference (52.5°C w/ 103AT), TS_TH4_TH5_TH6 = 011 38.5 39 39.5 %
VTS_HOT TS pin falling voltage threshold for TH6 comparator to transition from TS_WARM to TS_HOT.  Charging is suspended below this voltage. As Percentage to TS pin bias reference (50°C w/ 103AT), TS_TH4_TH5_TH6 = 100 or 101 40.7 41.2 41.7 %
As Percentage to TS pin bias reference (60°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 001, 010, 011, 110 or 111 33.9 34.4 34.9 %
VTS_HOTZ TS pin rising voltage threshold for TH6 comparator to transition from TS_HOT to TS_WARM. TS_WARM charging settings resume above this voltage. As Percentage to TS pin bias reference (47.5°C w/ 103AT), TS_TH4_TH5_TH6 = 100 or 101 42.0 42.5 43.0 %
As Percentage to TS pin bias reference (57.5°C w/ 103AT), TS_TH4_TH5_TH6 = 000, 001, 010, 011, 110 or 111 35.2 35.7 36.2 %
THERMISTOR COMPARATORS (OTG MODE)
VTS_OTG_COLD TS pin rising voltage threshold to transition from TS_OTG_NORMAL to TS_OTG_COLD. OTG suspended above this voltage. As Percentage to TS pin bias reference (–20°C w/ 103AT), TS_TH_OTG_COLD = 0 79.5 80.0 80.5 %
As Percentage to TS pin bias reference (–10°C w/ 103AT), TS_TH_OTG_COLD = 1 76.6 77.1 77.6 %
VTS_OTG_COLDZ TS pin falling voltage threshold to transition from TS_OTG_COLD to TS_OTG_NORMAL.  OTG resumes below this voltage. As Percentage to TS pin bias reference (–15°C w/ 103AT), TS_TH_OTG_COLD = 0 78.2 78.7 79.2 %
As Percentage to TS pin bias reference (–5°C w/ 103AT), TS_TH_OTG_COLD = 1 75.0 75.5 76.5 %
VTS_OTG_HOT TS pin falling voltage threshold to transition from TS_OTG_NORMAL to TS_OTG_HOT. OTG suspended below this voltage. As Percentage to TS pin bias reference (55°C w/ 103AT), TS_OTG_HOT = 00 37.2 37.7 38.2 %
As Percentage to TS pin bias reference (60°C w/ 103AT), TS_OTG_HOT = 01 33.9 34.4 34.9 %
As Percentage to TS pin bias reference (65°C w/ 103AT), TS_OTG_HOT = 10 30.8 31.3 31.8 %
VTS_OTG_HOTZ TS pin rising voltage threshold to transition from TS_OTG_HOT to TS_OTG_NORMAL.  OTG resumes above this threshold. As Percentage to TS pin bias reference (52.5°C w/ 103AT), TS_OTG_HOT = 00 38.5 39.0 39.5 %
As Percentage to TS pin bias reference (57.5°C w/ 103AT), TS_OTG_HOT = 01 35.2 35.7 36.2 %
As Percentage to TS pin bias reference (62.5°C w/ 103AT), TS_OTG_HOT = 10 32.0 32.5 33.0 %
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.35 1.5 1.65 MHz
MOSFET TURN-ON RESISTANCE
RQ1_ON VBUS to PMID on resistance Tj = –40°C-85°C 26 34 mΩ
RQ2_ON Buck high-side switching MOSFET turn on resistance between PMID and SW Tj = –40°C-85°C 55 78 mΩ
RQ3_ON Buck low-side switching MOSFET turn on resistance between SW and PGND Tj = –40°C-85°C 60 90 mΩ
OTG MODE CONVERTER
VOTG_RANGE Typical OTG mode voltage regulation range 3.8 9.6 V
VOTG_STEP Typical OTG mode voltage regulation step 80 mV
VOTG_ACC OTG mode voltage regulation accuracy IVBUS = 0A, VOTG = 9V –2 2 %
VOTG_ACC OTG mode voltage regulation accuracy IVBUS = 0A, VOTG = 5V –3 3 %
IOTG_RANGE Typical OTG mode current regulation range 0.1 2.4 A
IOTG_STEP Typical OTG mode current regulation step 20 mA
IOTG_ACC OTG mode current regulation accuracy IOTG = 1.8A –3 3 %
IOTG = 1.5A –5 5 %
IOTG = 0.5A –10 10 %
VOTG_UVP OTG mode undervoltage falling threshold at PMID 3.4 V
VOTG_VBUS_OVP OTG mode overvoltage rising threshold at VBUS 10.5 11.0 11.5 V
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.4 4.6 V
VVBUS = 9V, IREGN = 20mA 4.8 5.0 5.2 V
VREGNZ_OK REGN not good falling threshold Converter switching 3.2 V
Converter not switching 2.3 V
IREGN_LIM REGN LDO current limit VVBUS = 5V, VREGN = 4.3V 20 mA
ITS_BIAS_FAULT Rising threshold to transition from TSBIAS good condition to fault condition REGN=5V; ISINK applied on TS_BIAS pin 2.5 4.5 8 mA
ITS_BIAS_FAULTZ Falling threshold to transition from TSBIAS fault condition to good condition REGN=5V; ISINK applied on TS_BIAS pin 2 3.85 7 mA
ADC MEASUREMENT ACCURACY AND PERFORMANCE
tADC_CONV Conversion-time, Each Measurement ADC_SAMPLE = 00 24 ms
ADC_SAMPLE = 01 12 ms
ADC_SAMPLE = 10 6 ms
ADC_SAMPLE = 11 3 ms
ADCRES Effective Resolution ADC_SAMPLE = 00 11 12 bits
ADC_SAMPLE = 01 10 11 bits
ADC_SAMPLE = 10 9 10 bits
ADC_SAMPLE = 11 8 9 bits
ADC MEASUREMENT RANGE AND LSB
IBUS_ADC ADC Bus Current Reading (both forward and OTG) Range –4 4 A
LSB 2 mA
VBUS_ADC ADC VBUS Voltage Reading Range 0 18.00 V
LSB 3.97 mV
VPMID_ADC ADC PMID Voltage Reading Range 0 18.00 V
LSB 3.97 mV
VBAT_ADC ADC BAT Voltage Reading Range 0 5.572 V
LSB 1.99 mV
VSYS_ADC ADC SYS Voltage Reading Range 0 5.572 V
LSB 1.99 mV
IBAT_ADC ADC BAT Current Reading Range -7.5 4.0 A
LSB 4 mA
TS_ADC ADC TS Voltage Reading Range as a percent of REGN (–40 ℃ to 85 ℃ for 103AT) 20.9 83.2 %
ADC TS Voltage Reading LSB 0.0961 %
TDIE_ADC ADC Die Temperature Reading Range –40 140 °C
LSB 0.5 °C
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL 0.78 V
VIL Input low threshold level, SDA and SCL 0.42 V
VOL_SDA Output low threshold level Sink current = 5mA, 1.2V VDD 0.3 V
IBIAS High-level leakage current Pull up rail 1.8V 1 µA
CBUS Capacitive load for each bus line 400 pF
LOGIC OUTPUT PIN (INT, PG, STAT)
VOL Output low threshold level Sink current = 5mA 0.3 V
IOUT_BIAS High-level leakage current Pull up rail 1.8V 1 µA
LOGIC INPUT PIN (CE, QON)
VIH_CE Input high threshold level, /CE 0.78 V
VIL_CE Input low threshold level, /CE 0.4 V
IIN_BIAS_CE High-level leakage current, /CE Pull up rail 1.8V 1 µA
VIH_QON Input high threshold level, /QON 1.3 V
VIL_QON Input low threshold level, /QON 0.4 V
VQON Internal /QON pull up /QON is pulled up internally 5 V
RQON Internal /QON pull up resistance 250 kΩ