JAJSSD2A October 2023 – December 2023 BQ25638
PRODUCTION DATA
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BQ25638 provides an integrated 12-bit ADC for the host to monitor various system parameters. The ADC_RATE bit allows continuous conversion or one-shot behavior.
To enable the ADC, the EN_ADC bit must be set to ‘1’. The ADC is disabled by default (EN_ADC=0) to conserve power. The ADC is allowed to operate if either VBUS > VPOORSRC or VBAT > VBAT_LOWV is valid. If EN_ADC is set to ‘1’ before VBUS or VBAT reach their respective valid thresholds, then EN_ADC stays '0'. When the charger enters HIZ mode, the ADC is disabled, with EN_ADC set to '0'. The host can re-enable the ADC during HIZ mode by setting EN_ADC = 1. To minimize quiescent current during HIZ mode, the ADC should be disabled by setting EN_ADC=0.
At battery only condition, if the TS_ADC channel is enabled, the ADC will only operate when battery voltage is higher than 3.2V (the minimal value to turn on REGN), otherwise, the ADC will operate when the battery voltage is higher than VBAT_LOWV.
The ADC_DONE_STAT, ADC_DONE_FLAG bits will be set when a conversion is complete in one-shot mode only. During continuous conversion mode, the ADC_DONE_STAT, ADC_DONE_FLAG bits have no meaning and will remain at 0. In one-shot mode, the EN_ADC bit will be set to 0 at the completion of the conversion, at the same time as the ADC_DONE_FLAG bit is set. In continuous mode, the EN_ADC bit remains at 1 until the user disables the ADC by setting it to 0.
The device offers an optional ADCIN input to monitor the value of an external signal up-to 1V.