JAJSSD2A October 2023 – December 2023 BQ25638
PRODUCTION DATA
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Table 7-6 lists the memory-mapped registers for the BQ25638 registers. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x2 | REG0x02_Charge_Current_Limit | Charge Current Limit | Go |
0x4 | REG0x04_Charge_Voltage_Limit | Charge Voltage Limit | Go |
0x6 | REG0x06_Input_Current_Limit | Input Current Limit | Go |
0x8 | REG0x08_Input_Voltage_Limit | Input Voltage Limit | Go |
0xA | REG0x0A_IOTG_regulation | IOTG regulation | Go |
0xC | REG0x0C_VOTG_regulation | VOTG regulation | Go |
0xE | REG0x0E_Minimal_System_Voltage | Minimal System Voltage | Go |
0x10 | REG0x10_Precharge_Control | Precharge Control | Go |
0x12 | REG0x12_Termination_Control | Termination Control | Go |
0x14 | REG0x14_Charge_Timer_Control | Charge Timer Control | Go |
0x15 | REG0x15_Charger_Control_0 | Charger Control 0 | Go |
0x16 | REG0x16_Charger_Control_1 | Charger Control 1 | Go |
0x17 | REG0x17_Charger_Control_2 | Charger Control 2 | Go |
0x18 | REG0x18_Charger_Control_3 | Charger Control 3 | Go |
0x19 | REG0x19_Charger_Control_4 | Charger Control 4 | Go |
0x1A | REG0x1A_Charger_Control_5 | Charger Control 5 | Go |
0x1C | REG0x1C_NTC_Control_0 | NTC Control 0 | Go |
0x1D | REG0x1D_NTC_Control_1 | NTC Control 1 | Go |
0x1E | REG0x1E_NTC_Control_2 | NTC Control 2 | Go |
0x1F | REG0x1F_NTC_Control_3 | NTC Control 3 | Go |
0x20 | REG0x20_Charger_Status_0 | Charger Status 0 | Go |
0x21 | REG0x21_Charger_Status_1 | Charger Status 1 | Go |
0x22 | REG0x22_FAULT_Status | FAULT Status | Go |
0x23 | REG0x23_Charger_Flag_0 | Charger Flag 0 | Go |
0x24 | REG0x24_Charger_Flag_1 | Charger Flag 1 | Go |
0x25 | REG0x25_FAULT_Flag | FAULT Flag | Go |
0x26 | REG0x26_Charger_Mask_0 | Charger Mask 0 | Go |
0x27 | REG0x27_Charger_Mask_1 | Charger Mask 1 | Go |
0x28 | REG0x28_FAULT_Mask | FAULT Mask | Go |
0x29 | REG0x29_ICO_Current_Limit | ICO Current Limit | Go |
0x2B | REG0x2B_ADC_Control | ADC Control | Go |
0x2C | REG0x2C_ADC_Channel_Disable | ADC Channel Disable | Go |
0x2D | REG0x2D_IBUS_ADC | IBUS ADC | Go |
0x2F | REG0x2F_IBAT_ADC | IBAT ADC | Go |
0x31 | REG0x31_VBUS_ADC | VBUS ADC | Go |
0x33 | REG0x33_VPMID_ADC | VPMID ADC | Go |
0x35 | REG0x35_VBAT_ADC | VBAT ADC | Go |
0x37 | REG0x37_VSYS_ADC | VSYS ADC | Go |
0x39 | REG0x39_TS_ADC | TS ADC | Go |
0x3B | REG0x3B_TDIE_ADC | TDIE ADC | Go |
0x3D | REG0x3D_ADCIN_ADC | ADCIN ADC | Go |
0x3F | REG0x3F_Part_Information | Part Information | Go |
0x80 | REG0x80_Virtual_Control_0 | Virtual Control 0 | Go |
0x81 | REG0x81_Virtual_Control_1 | Virtual Control 1 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
REG0x02_Charge_Current_Limit is shown in Figure 7-17 and described in Table 7-8.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ICHG | ||||||
R-0x0 | R/W-0x19 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHG | RESERVED | ||||||
R/W-0x19 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:6 | ICHG | R/W | 0x19 | This 16-bit register follows the little-endian convention. Watchdog Timer expiration sets ICHG to 1/2 its previous value (rounded down) Reset by: REG_RESET WATCHDOG | Charge Current Regulation Limit: NOTE: When Q4_FULLON=1, this register has a minimum value of 320mA POR: 2000mA (19h) Range: 80mA-5040mA (1h-3Fh) Clamped Low Bit Step: 80mA |
5:0 | RESERVED | R | 0x0 | Reserved |
REG0x04_Charge_Voltage_Limit is shown in Figure 7-18 and described in Table 7-9.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VREG | ||||||
R-0x0 | R/W-0x1A4 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VREG | RESERVED | ||||||
R/W-0x1A4 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:3 | VREG | R/W | 0x1A4 | This 16-bit register follows the little-endian convention Reset by: REG_RESET | Battery Voltage Regulation Limit:
POR: 4200mV (1A4h) Range: 3500mV-4800mV (15Eh-1E0h) Clamped Low Clamped High Bit Step: 10mV |
2:0 | RESERVED | R | 0x0 | Reserved |
REG0x06_Input_Current_Limit is shown in Figure 7-19 and described in Table 7-10.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IINDPM | ||||||
R-0x0 | R/W-0xA0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IINDPM | RESERVED | ||||||
R/W-0xA0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:4 | IINDPM | R/W | 0xA0 | This 16-bit register follows the little-endian convention Reset by: REG_RESET Adapter Unplug | Input Current Regulation Limit: POR: 3200mA (A0h) Range: 100mA-3200mA (5h-A0h) Clamped Low Clamped High Bit Step: 20mA |
3:0 | RESERVED | R | 0x0 | Reserved |
REG0x08_Input_Voltage_Limit is shown in Figure 7-20 and described in Table 7-11.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VINDPM | ||||||
R-0x0 | R/W-0x6E | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VINDPM | RESERVED | ||||||
R/W-0x6E | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:14 | RESERVED | R | 0x0 | Reserved | |
13:5 | VINDPM | R/W | 0x6E | This 16-bit register follows the little-endian convention | Absolute Input Voltage Regulation Limit:
POR: 4400mV (6Eh) Range: 3800mV-16800mV (5Fh-1A4h) Clamped Low Clamped High Bit Step: 40mV |
4:0 | RESERVED | R | 0x0 | Reserved |
REG0x0A_IOTG_regulation is shown in Figure 7-21 and described in Table 7-12.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IOTG | ||||||
R-0x0 | R/W-0x4B | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOTG | RESERVED | ||||||
R/W-0x4B | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:4 | IOTG | R/W | 0x4B | This 16-bit register follows the little-endian convention Reset by: REG_RESET WATCHDOG | OTG mode current regulation limit:
POR: 1500mA (4Bh) Range: 100mA-3200mA (5h-A0h) Clamped Low Clamped High Bit Step: 20mA |
3:0 | RESERVED | R | 0x0 | Reserved |
REG0x0C_VOTG_regulation is shown in Figure 7-22 and described in Table 7-13.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VOTG | ||||||
R-0x0 | R/W-0x40 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VOTG | RESERVED | ||||||
R/W-0x40 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:13 | RESERVED | R | 0x0 | Reserved | |
12:6 | VOTG | R/W | 0x40 | This 16-bit register follows the little-endian convention Reset by: REG_RESET | OTG mode regulation voltage:
POR: 5120mV (40h) Range: 3840mV-9600mV (30h-78h) Clamped Low Clamped High Bit Step: 80mV |
5:0 | RESERVED | R | 0x0 | Reserved |
REG0x0E_Minimal_System_Voltage is shown in Figure 7-23 and described in Table 7-14.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VSYSMIN | ||||||
R-0x0 | R/W-0x2C | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VSYSMIN | RESERVED | ||||||
R/W-0x2C | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:6 | VSYSMIN | R/W | 0x2C | This 16-bit register follows the little-endian convention Reset by: REG_RESET | Minimal System Voltage:
POR: 3520mV (2Ch) Range: 2560mV-3840mV (20h-30h) Clamped Low Clamped High Bit Step: 80mV |
5:0 | RESERVED | R | 0x0 | Reserved |
REG0x10_Precharge_Control is shown in Figure 7-24 and described in Table 7-15.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IPRECHG | ||||||
R-0x0 | R/W-0xA | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPRECHG | RESERVED | ||||||
R/W-0xA | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:10 | RESERVED | R | 0x0 | Reserved | |
9:4 | IPRECHG | R/W | 0xA | This 16-bit register follows the little-endian convention Reset by: REG_RESET | Pre-charge current regulation limit: NOTE: When Q4_FULLON=1, this register has a minimum value of 320mA POR: 200mA (Ah) Range: 40mA-1000mA (2h-32h) Clamped Low Clamped High Bit Step: 20mA |
3:0 | RESERVED | R | 0x0 | Reserved |
REG0x12_Termination_Control is shown in Figure 7-25 and described in Table 7-16.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ITERM | ||||||
R-0x0 | R/W-0x14 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ITERM | RESERVED | ||||||
R/W-0x14 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:10 | RESERVED | R | 0x0 | Reserved | |
9:3 | ITERM | R/W | 0x14 | Reset by: REG_RESET | Termination Current Threshold: NOTE: When Q4_FULLON=1, this register has a minimum value of 240mA POR: 200mA (14h) Range: 30mA-1000mA (3h-64h) Clamped Low Clamped High Bit Step: 10mA |
2:0 | RESERVED | R | 0x0 | Reserved |
REG0x14_Charge_Timer_Control is shown in Figure 7-26 and described in Table 7-17.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_STAT | RESERVED | RESERVED | RESERVED | EN_TMR2X | EN_SAFETY_TMRS | PRECHG_TMR | CHG_TMR |
R/W-0x0 | R-0x0 | R-0x0 | R-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x0 | R/W-0x0 |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | DIS_STAT | R/W | 0x0 | Reset by: REG_RESET | Disable the /STAT pin output
0b = Enable (Default) 1b = Disable |
6 | RESERVED | R | 0x0 | Reserved | |
5 | RESERVED | R | 0x0 | Reserved | |
4 | RESERVED | R | 0x0 | Reserved | |
3 | EN_TMR2X | R/W | 0x1 | Reset by: REG_RESET | 2X charging timer control
0b = Trickle charge, pre-charge and fast charge timer not slowed by 2X during input DPM or thermal regulation. 1b = Trickle charge, pre-charge and fast charge timer slowed by 2X during input DPM or thermal regulation (default) |
2 | EN_SAFETY_TMRS | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Enable fast charge, pre-charge and trickle charge timers 0b = Disable 1b = Enable (default) |
1 | PRECHG_TMR | R/W | 0x0 | Reset by: REG_RESET | Pre-charge safety timer setting
0b = 2.3 hrs (default) 1b = 0.6 hrs |
0 | CHG_TMR | R/W | 0x0 | Reset by: REG_RESET | Fast charge safety timer setting
0b = 14 hrs (default) 1b = 27 hrs |
REG0x15_Charger_Control_0 is shown in Figure 7-27 and described in Table 7-18.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Q1_FULLON | Q4_FULLON | ITRICKLE | TOPOFF_TMR | EN_TERM | VINDPM_BAT_TRACK | VRECHG | |
R/W-0x0 | R/W-0x0 | R/W-0x1 | R/W-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x0 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | Q1_FULLON | R/W | 0x0 | Forces RBFET (Q1) into low resistance state (15 mΩ) , regardless of IINDPM setting. 0b = RBFET RDSON determined by IINDPM setting 1b = RBFET RDSON is always 15 mOhm | |
6 | Q4_FULLON | R/W | 0x0 | Forces BATFET (Q4) into low resistance state (7 mΩ), regardless of ICHG setting. 0b = BATFET RDSON determined by charge current 1b = BATFET RDSON is always 7 mOhm | |
5 | ITRICKLE | R/W | 0x1 | When Q4_FULLON, this setting is forced to 80mA Reset by: REG_RESET | Trickle charging current setting:
0b = 20mA 1b = 80mA |
4:3 | TOPOFF_TMR | R/W | 0x0 | Reset by: REG_RESET | Top-off timer control:
00b = Disabled (default) 01b = 17.5 mins 10b = 35 mins 11b = 52 mins |
2 | EN_TERM | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Enable termination
0b = Disable 1b = Enable (default) |
1 | VINDPM_BAT_TRACK | R/W | 0x1 | Reset by: REG_RESET | Sets VINDPM to track BAT voltage. Actual VINDPM is higher of the VINDPM register value and VBAT + VINDPM_BAT_TRACK.
0b = Disable function (VINDPM set by register) 1b = VBAT + 350 mV (default) |
0 | VRECHG | R/W | 0x0 | Reset by: REG_RESET | Battery Recharge Threshold Offset (Below VREG)
0b = 100mV (default) 1b = 200mV |
REG0x16_Charger_Control_1 is shown in Figure 7-28 and described in Table 7-19.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_AUTO_IBAT_DSCHG | FORCE_IBAT_DSCHG | EN_CHG | EN_HIZ | FORCE_PMID_DSCHG | WD_RST | WATCHDOG | |
R/W-0x1 | R/W-0x0 | R/W-0x1 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | EN_AUTO_IBAT_DSCHG | R/W | 0x1 | Reset by: REG_RESET | Enable the auto battery discharging during the battery OVP fault
0b = The charger will NOT apply a discharging current on BAT during battery OVP triggered 1b = The charger will apply a discharging current on BAT during battery OVP triggered (default) |
6 | FORCE_IBAT_DSCHG | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Enable BAT pull down current source
0b = Disable 1b = Enable |
5 | EN_CHG | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Charger enable configuration
0b = Charge Disable 1b = Charge Enable (default) |
4 | EN_HIZ | R/W | 0x0 | Reset by: REG_RESET WATCHDOG Adapter Plug In | Enable HIZ mode. This bit will be reset to 0, when the adapter is plugged in at VBUS. 0b = Disable (default) 1b = Enable |
3 | FORCE_PMID_DSCHG | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Enable PMID pull down current source (~30mA)
0b = Disable 1b = Enable |
2 | WD_RST | R/W | 0x0 | Reset by: REG_RESET | I2C watch dog timer reset
0b = Normal (default) 1b = Reset (this bit goes back to 0 after timer reset) |
1:0 | WATCHDOG | R/W | 0x1 | Reset by: REG_RESET | Watchdog timer setting
00b = Disable 01b = 40s (default) 10b = 80s 11b = 160s |
REG0x17_Charger_Control_2 is shown in Figure 7-29 and described in Table 7-20.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_RST | TREG | EN_DITHER | SET_CONV_STRN | SET_BATFET_STRN | VBUS_OVP | ||
R/W-0x0 | R/W-0x1 | R/W-0x0 | R/W-0x3 | R/W-0x1 | R/W-0x1 | ||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | REG_RST | R/W | 0x0 | Reset registers to default values and reset timer Value resets to 0 after reset completes. 0b = Not reset (default) 1b = Reset | |
6 | TREG | R/W | 0x1 | Reset by: REG_RESET | Thermal regulation thresholds.
0b = 60°C 1b = 120°C |
5:4 | EN_DITHER | R/W | 0x0 | Reset by: REG_RESET | Frequency Dither configuration:
00b = Disable 01b = 1X 10b = 2X 11b = 3X |
3:2 | SET_CONV_STRN | R/W | 0x3 | Reset by: REG_RESET | Adjust the drive strength of the converter to adjust efficiency versus EMI. 00b = reduce drive strength three steps 01b = reduce drive strength two steps 10b = reduce drive strength one step 11b = maximum drive strength (default) |
1 | SET_BATFET_STRN | R/W | 0x1 | Reset by: REG_RESET | Adjust the drive strength of the BATFET to control speed of turn on and turn off. 0b = reduce drive strength 1b = maximum drive strength (default) |
0 | VBUS_OVP | R/W | 0x1 | Reset by: REG_RESET | Set VBUS overvoltage protection threshold
0b = 6.3V 1b = 18.5V |
REG0x18_Charger_Control_3 is shown in Figure 7-30 and described in Table 7-21.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN_OTG | DIS_PFM_OTG | DIS_PFM_FWD | BATFET_CTRL_WVBUS | BATFET_DLY | BATFET_CTRL | |
R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | R/W-0x0 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved | |
6 | EN_OTG | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | OTG mode control
0b = OTG Disable (default) 1b = OTG Enable |
5 | DIS_PFM_OTG | R/W | 0x0 | Reset by: REG_RESET | Disable PFM in OTG boost mode
0b = Enable (Default) 1b = Disable |
4 | DIS_PFM_FWD | R/W | 0x0 | Reset by: REG_RESET | Disable PFM in forward buck mode
0b = Enable (Default) 1b = Disable |
3 | BATFET_CTRL_WVBUS | R/W | 0x0 | Start system power reset with or without adapter present.
0b = Start system power reset after adapter is removed from VBUS. (default) 1b = Start system power reset whether or not adapter is present on VBUS. | |
2 | BATFET_DLY | R/W | 0x1 | Reset by: REG_RESET | Delay time added to the taking action in bits [1:0] of the BATFET_CTRL
0b = Add 24ms delay 1b = Add 12s delay |
1:0 | BATFET_CTRL | R/W | 0x0 | Reset by: REG_RESET | BATFET control The control logic of the BATFET to force the device enter different modes. 00b = Idle 01b = Shutdown Mode 10b = Ultra-Low Power Mode 11b = System Power Reset |
REG0x19_Charger_Control_4 is shown in Figure 7-31 and described in Table 7-22.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IBAT_PK | VBAT_UVLO | VBAT_OTG_MIN | RESERVED | EN_EXT_ILIM | FORCE_ICO | EN_ICO | |
R/W-0x2 | R/W-0x0 | R/W-0x0 | R-0x0 | R/W-0x1 | R/W-0x0 | R/W-0x1 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | IBAT_PK | R/W | 0x2 | Reset by: REG_RESET | Battery discharging over current protection threshold setting 00b = 3A 01b = 6A 10b = 9A 11b = Reserved |
5 | VBAT_UVLO | R/W | 0x0 | Reset by: REG_RESET | Select the VBAT UVLO falling thresholds
0b = 2.2V (default) 1b = 1.8V |
4 | VBAT_OTG_MIN | R/W | 0x0 | Reset by: REG_RESET | Select the minimal battery voltage to start the OTG mode
0b = 3V rising / 2.8 falling (default) 1b = 2.4V rising / 2.2 falling |
3 | RESERVED | R | 0x0 | Reserved | |
2 | EN_EXT_ILIM | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Enable External ILIM pin input current regulation
0b = Disable 1b = Enable |
1 | FORCE_ICO | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Force Start Input Current Optimizer (ICO): Note: This bit can only be set and always returns to 0 after ICO starts. This bit is only valid when EN_ICO = 1 0b = Do not force ICO 1b = Force ICO start |
0 | EN_ICO | R/W | 0x1 | Reset by: REG_RESET | Input Current Optimization (ICO) Algorithm Control:
0b = Disable ICO 1b = Enable ICO |
REG0x1A_Charger_Control_5 is shown in Figure 7-32 and described in Table 7-23.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PG_TH | TQON_RST | TSM_EXIT | FORCE_ISYS_DSCHG | BATLOWV | |||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:5 | PG_TH | R/W | 0x0 | Reset by: REG_RESET | Programmable PG indicator falling threshold:
000b = 3.7V 001b = 7.4V 010b = 8V 011b = 10.4V 100b = 11V 101b = 13.4V 110b = 14V 111b = Reserved |
4 | TQON_RST | R/W | 0x0 | System Reset (tQON_RST) control:
0b = 11s 1b = 21s | |
3 | TSM_EXIT | R/W | 0x0 | Ultra-Low Power Mode exit (tSM_EXIT) control:
0b = 700ms 1b = 10.5s | |
2 | FORCE_ISYS_DSCHG | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Enable SYS pull down current source
0b = Disable 1b = Enable |
1:0 | BATLOWV | R/W | 0x0 | Battery precharge to fast-charge threshold:
00b = 3.0V 01b = 2.8V 10b = 2.7V 11b = 2.5V |
REG0x1C_NTC_Control_0 is shown in Figure 7-33 and described in Table 7-24.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_IGNORE | CHG_RATE | TS_TH_OTG_HOT | TS_TH_OTG_COLD | TS_TH1 | TS_TH6 | ||
R/W-0x0 | R/W-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x1 | R/W-0x1 | ||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | TS_IGNORE | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Ignore the TS feedback, the charger will consider the TS is always good to allow charging and OTG modes, TS_STAT always reports TS_NORMAL 0b = Not ignore 1b = Ignore |
6:5 | CHG_RATE | R/W | 0x0 | Reset by: REG_RESET | The charge rate used when device is in fast-charge. Once device enters JEITA region where charge current is reduced, the resulting current is = (ICHG * foldback ratio)/CHG_RATE:
00b = 1C 01b = 2C 10b = 4C 11b = 6C |
4:3 | TS_TH_OTG_HOT | R/W | 0x1 | Reset by: REG_RESET | OTG Mode TS_HOT falling voltage threshold (as a percentage of REGN) to transition from normal operation into suspended OTG mode. 00b = 55°C 01b = 60°C 10b = 65°C 11b = Disable |
2 | TS_TH_OTG_COLD | R/W | 0x1 | Reset by: REG_RESET | OTG Mode TS_COLD rising voltage threshold (as a percentage of REGN) to transition from normal operation into suspended OTG mode. 0b = -10°C 1b = -20°C |
1 | TS_TH1 | R/W | 0x1 | Reset by: REG_RESET | TS TH1 comparator falling temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 0b = -5°C 1b = 0°C |
0 | TS_TH6 | R/W | 0x1 | Reset by: REG_RESET | TS TH6 comparator rising temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 0b = 55°C 1b = 60°C |
REG0x1D_NTC_Control_1 is shown in Figure 7-34 and described in Table 7-25.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_TH2 | TS_TH3 | TS_TH4 | TS_TH5 | ||||
R/W-0x2 | R/W-0x0 | R/W-0x1 | R/W-0x1 | ||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | TS_TH2 | R/W | 0x2 | Reset by: REG_RESET | TS TH2 comparator falling temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 00b = 5°C 01b = 7.5°C 10b = 10°C 11b = 12.5°C |
5:4 | TS_TH3 | R/W | 0x0 | Reset by: REG_RESET | TS TH3 comparator falling temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 00b = 15°C 01b = 17.5°C 10b = 20°C 11b = 22.5°C |
3:2 | TS_TH4 | R/W | 0x1 | Reset by: REG_RESET | TS TH4 comparator rising temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 00b = 32.5°C 01b = 35°C 10b = 37.5°C 11b = 40°C |
1:0 | TS_TH5 | R/W | 0x1 | Reset by: REG_RESET | TS TH5 comparator rising temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ 00b = 42.5°C 01b = 45°C 10b = 47.5°C 11b = 50°C |
REG0x1E_NTC_Control_2 is shown in Figure 7-35 and described in Table 7-26.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_VSET_WARM | TS_ISET_WARM | TS_VSET_PREWARM | TS_ISET_PREWARM | ||||
R/W-0x1 | R/W-0x3 | R/W-0x3 | R/W-0x3 | ||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | TS_VSET_WARM | R/W | 0x1 | Reset by: REG_RESET | TS_WARM (TH5 - TH6) Voltage Setting
00b = Set VREG to VREG-300mV 01b = Set VREG to VREG-200mV 10b = Set VREG to VREG-100mV 11b = VREG unchanged |
5:4 | TS_ISET_WARM | R/W | 0x3 | Reset by: REG_RESET | TS_WARM (TH5 - TH6) Current Setting
00b = Charge Suspend 01b = Set ICHG to 20% 10b = Set ICHG to 40% 11b = ICHG unchanged |
3:2 | TS_VSET_PREWARM | R/W | 0x3 | Reset by: REG_RESET | TS_PREWARM (TH4 - TH5) Voltage Setting
00b = Set VREG to VREG-300mV 01b = Set VREG to VREG-200mV 10b = Set VREG to VREG-100mV 11b = VREG unchanged |
1:0 | TS_ISET_PREWARM | R/W | 0x3 | Reset by: REG_RESET | TS_PREWARM (TH4 - TH5) Current Setting
00b = Charge Suspend 01b = Set ICHG to 20% 10b = Set ICHG to 40% 11b = ICHG unchanged |
REG0x1F_NTC_Control_3 is shown in Figure 7-36 and described in Table 7-27.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_VSET_COOL | TS_ISET_COOL | TS_VSET_PRECOOL | TS_ISET_PRECOOL | ||||
R/W-0x3 | R/W-0x1 | R/W-0x3 | R/W-0x3 | ||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | TS_VSET_COOL | R/W | 0x3 | Reset by: REG_RESET | TS_COOL (TH1 - TH2) Voltage Setting
00b = Set VREG to VREG-300mV 01b = Set VREG to VREG-200mV 10b = Set VREG to VREG-100mV 11b = VREG unchanged |
5:4 | TS_ISET_COOL | R/W | 0x1 | Reset by: REG_RESET | TS_COOL (TH1 - TH2) Current Setting
00b = Charge Suspend 01b = Set ICHG to 20% 10b = Set ICHG to 40% 11b = ICHG unchanged |
3:2 | TS_VSET_PRECOOL | R/W | 0x3 | Reset by: REG_RESET | TS_PRECOOL (TH2 - TH3) Voltage Setting:
00b = Set VREG to VREG-300mV 01b = Set VREG to VREG-200mV 10b = Set VREG to VREG-100mV 11b = VREG unchanged |
1:0 | TS_ISET_PRECOOL | R/W | 0x3 | Reset by: REG_RESET | TS_PRECOOL (TH2 - TH3) Current Setting:
00b = Charge Suspend 01b = Set ICHG to 20% 10b = Set ICHG to 40% 11b = ICHG unchanged |
REG0x20_Charger_Status_0 is shown in Figure 7-37 and described in Table 7-28.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PG_STAT | ADC_DONE_STAT | TREG_STAT | VSYS_STAT | IINDPM_STAT | VINDPM_STAT | SAFETY_TMR_STAT | WD_STAT |
R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PG_STAT | R | 0x0 | Power Good Indicator Status:
0b = VBUS below PG_TH 1b = VBUS above PG_TH |
6 | ADC_DONE_STAT | R | 0x0 | ADC Conversion Status (in one-shot mode only) Note: Always reads 0 in continuous mode 0b = Conversion not complete 1b = Conversion complete |
5 | TREG_STAT | R | 0x0 | IC Thermal regulation status
0b = Normal 1b = Device in thermal regulation |
4 | VSYS_STAT | R | 0x0 | VSYS Regulation Status (forward mode)
0b = Not in VSYSMIN regulation (BAT>VSYSMIN) 1b = In VSYSMIN regulation (BAT<VSYSMIN) |
3 | IINDPM_STAT | R | 0x0 | IINDPM status (forward mode) or IOTG status (OTG mode)
0b = Normal 1b = In IINDPM regulation or IOTG regulation |
2 | VINDPM_STAT | R | 0x0 | VINDPM status (forward mode) or VOTG status (OTG mode, backup mode)
0b = Normal 1b = In VINDPM regulation or VOTG regualtion |
1 | SAFETY_TMR_STAT | R | 0x0 | Fast charge, trickle charge and pre-charge timer status
0b = Normal 1b = Safety timer expired |
0 | WD_STAT | R | 0x0 | I2C watch dog timer status
0b = Normal 1b = WD timer expired |
REG0x21_Charger_Status_1 is shown in Figure 7-38 and described in Table 7-29.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICO_STAT | CHG_STAT | VBUS_STAT | |||||
R-0x0 | R-0x0 | R-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | ICO_STAT | R | 0x0 | Input Current Optimizer (ICO) Status:
00b = ICO Disabled 01b = ICO Optimization in Progress 10b = Maximum input current detected 11b = ICO Routine Suspended |
5:3 | CHG_STAT | R | 0x0 | Charge Status:
000b = Not Charging 001b = Trickle Charge 010b = Pre-charge 011b = Fast Charge (CC) 100b = Taper Charge (CV) 101b = Reserved 110b = Top-off Timer Active Charging 111b = Charge Termination Done |
2:0 | VBUS_STAT | R | 0x0 | VBUS status:
000b = Not powered from VBUS 100b = Unknown adaptor (IINDPM Default) 111b = In boost OTG |
REG0x22_FAULT_Status is shown in Figure 7-39 and described in Table 7-30.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_FAULT_STAT | BAT_FAULT_STAT | VSYS_FAULT_STAT | OTG_FAULT_STAT | TSHUT_STAT | TS_STAT | ||
R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VBUS_FAULT_STAT | R | 0x0 | VBUS over-voltage status
0b = Normal 1b = Device in over voltage protection |
6 | BAT_FAULT_STAT | R | 0x0 | Battery fault status
0b = Normal 1b = Dead or over-voltage battery detected |
5 | VSYS_FAULT_STAT | R | 0x0 | VSYS under voltage and over voltage status
0b = Normal 1b = SYS in SYS short circuit or over voltage |
4 | OTG_FAULT_STAT | R | 0x0 | OTG under voltage and over voltage status.
0b = Normal 1b = Fault Detected |
3 | TSHUT_STAT | R | 0x0 | IC temperature shutdown status
0b = Normal 1b = Device in thermal shutdown protection |
2:0 | TS_STAT | R | 0x0 | The TS temperature zone.
000b = TS_NORMAL 001b = TS_COLD or TS_OTG_COLD 010b = TS_HOT or TS_OTG_HOT 011b = TS_COOL 100b = TS_WARM 101b = TS_PRECOOL 110b = TS_PREWARM 111b = RESERVED |
REG0x23_Charger_Flag_0 is shown in Figure 7-40 and described in Table 7-31.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PG_FLAG | ADC_DONE_FLAG | TREG_FLAG | VSYS_FLAG | IINDPM_FLAG | VINDPM_FLAG | SAFETY_TMR_FLAG | WD_FLAG |
R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PG_FLAG | R | 0x0 | Power Good indicator flag:
Access: R (ClearOnRead) 0b = Normal 1b = PG status changed |
6 | ADC_DONE_FLAG | R | 0x0 | ADC convertersion flag (only in one-shot mode)
Access: R (ClearOnRead) 0b = Conversion not completed 1b = Conversion completed |
5 | TREG_FLAG | R | 0x0 | IC Thermal regulation flag
Access: R (ClearOnRead) 0b = Normal 1b = TREG signal rising threshold detected |
4 | VSYS_FLAG | R | 0x0 | VSYS min regulation flag
Access: R (ClearOnRead) 0b = Normal 1b = Entered or exited VSYS min regulation |
3 | IINDPM_FLAG | R | 0x0 | IINDPM or IOTG flag
Access: R (ClearOnRead) 0b = Normal 1b = IINDPM signal rising edge detected |
2 | VINDPM_FLAG | R | 0x0 | VINDPM or VOTG flag
Access: R (ClearOnRead) 0b = Normal 1b = VINDPM regulation signal rising edge detected |
1 | SAFETY_TMR_FLAG | R | 0x0 | Fast charge, trickle charge and pre-charge timer flag
Access: R (ClearOnRead) 0b = Normal 1b = Fast chargeg timer expired rising edge detected |
0 | WD_FLAG | R | 0x0 | I2C watchdog timer flag
Access: R (ClearOnRead) 0b = Normal 1b = WD timer signal rising edge detected |
REG0x24_Charger_Flag_1 is shown in Figure 7-41 and described in Table 7-32.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ICO_FLAG | RESERVED | CHG_FLAG | RESERVED | VBUS_FLAG | ||
R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | ICO_FLAG | R | 0x0 | Input Current Optimizer (ICO) flag
Access: R (ClearOnRead) 0b = Normal 1b = ICO_STAT[1:0] changed (transition to any state) |
5:4 | RESERVED | R | 0x0 | Reserved |
3 | CHG_FLAG | R | 0x0 | Charge status flag
Access: R (ClearOnRead) 0b = Normal 1b = Charge status changed |
2:1 | RESERVED | R | 0x0 | Reserved |
0 | VBUS_FLAG | R | 0x0 | VBUS status flag
Access: R (ClearOnRead) 0b = Normal 1b = VBUS status changed |
REG0x25_FAULT_Flag is shown in Figure 7-42 and described in Table 7-33.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_FAULT_FLAG | BAT_FAULT_FLAG | VSYS_FAULT_FLAG | OTG_FAULT_FLAG | TSHUT_FLAG | RESERVED | TS_FLAG | |
R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VBUS_FAULT_FLAG | R | 0x0 | VBUS over-voltage flag
Access: R (ClearOnRead) 0b = Normal 1b = Entered VBUS OVP |
6 | BAT_FAULT_FLAG | R | 0x0 | VBAT over-voltage flag
Access: R (ClearOnRead) 0b = Normal 1b = Entered VBAT OVP |
5 | VSYS_FAULT_FLAG | R | 0x0 | VSYS over voltage and SYS short flag
Access: R (ClearOnRead) 0b = Normal 1b = Stopped switching due to system over-voltage or SYS short fault |
4 | OTG_FAULT_FLAG | R | 0x0 | OTG under voltage and over voltage flag
Access: R (ClearOnRead) 0b = Normal 1b = Stopped OTG due to VBUS under voltage or over voltage fault |
3 | TSHUT_FLAG | R | 0x0 | IC thermal shutdown flag
Access: R (ClearOnRead) 0b = Normal 1b = TS shutdown signal rising threshold detected |
2:1 | RESERVED | R | 0x0 | Reserved |
0 | TS_FLAG | R | 0x0 | TS status flag
Access: R (ClearOnRead) 0b = Normal 1b = A change to TS status was detected |
REG0x26_Charger_Mask_0 is shown in Figure 7-43 and described in Table 7-34.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PG_MASK | ADC_DONE_MASK | TREG_MASK | VSYS_MASK | IINDPM_MASK | VINDPM_MASK | SAFETY_TMR_MASK | WD_MASK |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | PG_MASK | R/W | 0x0 | Reset by: REG_RESET | Power Good indicator INT mask
0b = PG status change does produce INT pulse 1b = PG status change does not produce INT pulse |
6 | ADC_DONE_MASK | R/W | 0x0 | Reset by: REG_RESET | ADC conversion INT mask (only in one-shot mode)
0b = ADC conversion done does produce INT pulse 1b = ADC conversion done does not produce INT pulse |
5 | TREG_MASK | R/W | 0x0 | Reset by: REG_RESET | IC thermal regulation INT mask
0b = Entering TREG does produce INT 1b = Entering TREG does not produce INT |
4 | VSYS_MASK | R/W | 0x0 | Reset by: REG_RESET | VSYS min regulation INT mask
0b = Enter or exit VSYSMIN regulation does produce INT pulse 1b = Enter or exit VSYSMIN regulation does not produce INT pulse |
3 | IINDPM_MASK | R/W | 0x0 | Reset by: REG_RESET | IINDPM or IOTG INT mask
0b = Enter IINDPM or IOTG does produce INT pulse 1b = Enter IINDPM or IOTG does not produce INT pulse |
2 | VINDPM_MASK | R/W | 0x0 | Reset by: REG_RESET | VINDPM or VOTG INT mask
0b = Enter VINDPM does produce INT pulse 1b = Enter VINDPM does not produce INT pulse |
1 | SAFETY_TMR_MASK | R/W | 0x0 | Reset by: REG_RESET | Fast charge, trickle charge and pre-charge timer INT mask
0b = Fast charge, trickle charge or pre-charge timer expiration does produce INT 1b = Fast charge, trickle charge or pre-charge timer expiration does not produce INT |
0 | WD_MASK | R/W | 0x0 | Reset by: REG_RESET | I2C watch dog timer INT mask
0b = I2C watch dog timer expired does produce INT pulse 1b = I2C watch dog timer expired does not produce INT pulse |
REG0x27_Charger_Mask_1 is shown in Figure 7-44 and described in Table 7-35.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ICO_MASK | RESERVED | CHG_MASK | RESERVED | VBUS_MASK | ||
R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved | |
6 | ICO_MASK | R/W | 0x0 | Reset by: REG_RESET | Input Current Optimizer (ICO) INT mask
0b = ICO_STAT change does produce INT 1b = ICO_STAT change does not produce INT |
5:4 | RESERVED | R | 0x0 | Reserved | |
3 | CHG_MASK | R/W | 0x0 | Reset by: REG_RESET | Charge status INT mask
0b = Charging status change does produce INT 1b = Charging status change does not produce INT |
2:1 | RESERVED | R | 0x0 | Reserved | |
0 | VBUS_MASK | R/W | 0x0 | Reset by: REG_RESET | VBUS status INT mask
0b = VBUS status change does produce INT 1b = VBUS status change does not produce INT |
REG0x28_FAULT_Mask is shown in Figure 7-45 and described in Table 7-36.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_FAULT_MASK | BAT_FAULT_MASK | VSYS_FAULT_MASK | OTG_FAULT_MASK | TSHUT_MASK | RESERVED | TS_MASK | |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | VBUS_FAULT_MASK | R/W | 0x0 | Reset by: REG_RESET | VBUS over-voltage INT mask
0b = Entering VBUS OVP does produce INT 1b = Entering VBUS OVP does not produce INT |
6 | BAT_FAULT_MASK | R/W | 0x0 | Reset by: REG_RESET | IBAT/VBAT over-current/over-voltage INT mask
0b = Entering IBAT OCP or VBAT OVP does produce INT 1b = Entering IBAT OCP or VBAT OVP does not produce INT |
5 | VSYS_FAULT_MASK | R/W | 0x0 | Reset by: REG_RESET | VSYS over voltage and SYS short INT mask
0b = System over-voltage or SYS short fault does produce INT 1b = Neither system over voltage nor SYS short fault produces INT |
4 | OTG_FAULT_MASK | R/W | 0x0 | Reset by: REG_RESET | OTG under voltage and over voltage INT mask
0b = OTG VBUS under voltage or over voltage fault does produce INT 1b = Neither OTG VBUS under voltage nor over voltage fault produces INT |
3 | TSHUT_MASK | R/W | 0x0 | Reset by: REG_RESET | IC thermal shutdown INT mask
0b = TSHUT does produce INT 1b = TSHUT does not produce INT |
2:1 | RESERVED | R | 0x0 | Reserved | |
0 | TS_MASK | R/W | 0x0 | Reset by: REG_RESET | Temperature charging profile INT mask
0b = A change to TS temperature zone does produce INT 1b = A change to the TS temperature zone does not produce INT |
REG0x29_ICO_Current_Limit is shown in Figure 7-46 and described in Table 7-37.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ICO_IINDPM | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICO_IINDPM | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved | |
11:4 | ICO_IINDPM | R | 0x0 | This 16-bit register follows the little-endian convention Reset by: Adapter Unplug | Optimized Input Current Limit when ICO is enabled:
POR: 0mA (0h) Range: 100mA-3200mA (5h-A0h) Clamped Low Clamped High Bit Step: 20mA |
3:0 | RESERVED | R | 0x0 | Reserved |
REG0x2B_ADC_Control is shown in Figure 7-47 and described in Table 7-38.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_ADC | ADC_RATE | ADC_SAMPLE | ADC_AVG | ADC_AVG_INIT | RESERVED | DIS_ADCIN_ADC | |
R/W-0x0 | R/W-0x0 | R/W-0x3 | R/W-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | EN_ADC | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | ADC Control
0b = Disable (default) 1b = Enable |
6 | ADC_RATE | R/W | 0x0 | Reset by: REG_RESET | ADC conversion rate control
0b = Continuous conversion (default) 1b = One shot conversion |
5:4 | ADC_SAMPLE | R/W | 0x3 | Reset by: REG_RESET | ADC sample speed
00b = 11 bit effective resolution 01b = 10 bit effective resolution 10b = 9 bit effective resolution 11b = 8 bit effective resolution (default) |
3 | ADC_AVG | R/W | 0x0 | Reset by: REG_RESET | ADC average control
0b = Single value (default) 1b = Running average |
2 | ADC_AVG_INIT | R/W | 0x0 | Reset by: REG_RESET | ADC acerage initial value control
0b = Start average using the existing register value 1b = Start average using a new ADC conversion |
1 | RESERVED | R | 0x0 | Reserved | |
0 | DIS_ADCIN_ADC | R/W | 0x0 | Reset by: REG_RESET | ADCIN ADC channel disable
0b = Enable 1b = Disable |
REG0x2C_ADC_Channel_Disable is shown in Figure 7-48 and described in Table 7-39.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_IBUS_ADC | DIS_IBAT_ADC | DIS_VBUS_ADC | DIS_VBAT_ADC | DIS_VSYS_ADC | DIS_TS_ADC | DIS_TDIE_ADC | DIS_VPMID_ADC |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | DIS_IBUS_ADC | R/W | 0x0 | Reset by: REG_RESET | IBUS ADC channel disable
0b = Enable 1b = Disable |
6 | DIS_IBAT_ADC | R/W | 0x0 | Reset by: REG_RESET | IBAT ADC control
0b = Enable 1b = Disable |
5 | DIS_VBUS_ADC | R/W | 0x0 | Reset by: REG_RESET | VBUS ADC control
0b = Enable 1b = Disable |
4 | DIS_VBAT_ADC | R/W | 0x0 | Reset by: REG_RESET | VBAT ADC control
0b = Enable 1b = Disable |
3 | DIS_VSYS_ADC | R/W | 0x0 | Reset by: REG_RESET | VSYS ADC control
0b = Enable 1b = Disable |
2 | DIS_TS_ADC | R/W | 0x0 | Reset by: REG_RESET | TS ADC control
0b = Enable 1b = Disable |
1 | DIS_TDIE_ADC | R/W | 0x0 | Reset by: REG_RESET | TDIE ADC control
0b = Enable 1b = Disable |
0 | DIS_VPMID_ADC | R/W | 0x0 | Reset by: REG_RESET | VPMID ADC control
0b = Enable 1b = Disable |
REG0x2D_IBUS_ADC is shown in Figure 7-49 and described in Table 7-40.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IBUS_ADC | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IBUS_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:1 | IBUS_ADC | R | 0x0 | IBUS ADC reading Reported in 2 's Complement. When the current is flowing from VBUS to PMID, IBUS ADC reports positive value, and when the current is flowing from PMID to VBUS, IBUS ADC reports negative value. POR: 0mA(0h) Format: 2s Complement Range: -5000mA - 5000mA (7830h-7D0h) Clamped Low Clamped High Bit Step: 2.5mA |
0 | RESERVED | R | 0x0 | Reserved |
REG0x2F_IBAT_ADC is shown in Figure 7-50 and described in Table 7-41.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IBAT_ADC | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IBAT_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:3 | IBAT_ADC | R | 0x0 | IBAT ADC reading Reported in 2 's Complement. The IBAT ADC reports positive value for the battery charging current, and negative value for the battery discharging current. POR: 0mA (0h) Format: 2s Complement Range: -10000mA-5025mA (1830h-3EDh) Clamped Low Clamped High Bit Step: 5mA |
2:0 | RESERVED | R | 0x0 | Reserved |
REG0x31_VBUS_ADC is shown in Figure 7-51 and described in Table 7-42.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUS_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUS_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | Reserved |
14:2 | VBUS_ADC | R | 0x0 | VBUS ADC reading
POR: 0mV (0h) Range: 0mV-20000mV (0h-FA0h) Clamped High Bit Step: 5mV |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x33_VPMID_ADC is shown in Figure 7-52 and described in Table 7-43.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VPMID_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VPMID_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0x0 | Reserved |
14:2 | VPMID_ADC | R | 0x0 | VPMID ADC reading
POR: 0mV (0h) Range: 0mV-20000mV (0h-FA0h) Clamped High Bit Step: 5mV |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x35_VBAT_ADC is shown in Figure 7-53 and described in Table 7-44.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBAT_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBAT_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | RESERVED | R | 0x0 | Reserved |
12:1 | VBAT_ADC | R | 0x0 | VBAT ADC reading
POR: 0mV(0h) Range: 0mV - 5000mV (0h-FA0h) Clamped High Bit Step: 1.25mV |
0 | RESERVED | R | 0x0 | Reserved |
REG0x37_VSYS_ADC is shown in Figure 7-54 and described in Table 7-45.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VSYS_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VSYS_ADC | RESERVED | ||||||
R-0x0 | R-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | RESERVED | R | 0x0 | Reserved |
12:1 | VSYS_ADC | R | 0x0 | VSYS ADC reading
POR: 0mV(0h) Range: 0mV - 5000mV (0h-FA0h) Clamped High Bit Step: 1.25mV |
0 | RESERVED | R | 0x0 | Reserved |
REG0x39_TS_ADC is shown in Figure 7-55 and described in Table 7-46.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TS_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_ADC | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved |
11:0 | TS_ADC | R | 0x0 | TS ADC reading
POR: 0%(0h) Range: 0% - 99.90234375% (0h-3FFh) Clamped High Bit Step: 0.09765625% |
REG0x3B_TDIE_ADC is shown in Figure 7-56 and described in Table 7-47.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TDIE_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDIE_ADC | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved |
11:0 | TDIE_ADC | R | 0x0 | TDIE ADC reading Reported in 2 's Complement. POR: 0°C(0h) Format: 2s Complement Range: -40°C - 150°C (FB0h-12Ch) Clamped Low Clamped High Bit Step: 0.5°C |
REG0x3D_ADCIN_ADC is shown in Figure 7-57 and described in Table 7-48.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADCIN_ADC | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCIN_ADC | |||||||
R-0x0 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0x0 | Reserved |
11:0 | ADCIN_ADC | R | 0x0 | ADCIN ADC reading
POR: 0mV(0h) Range: 0mV - 1000mV (0h-FA0h) Clamped High Bit Step: 0.25mV |
REG0x3F_Part_Information is shown in Figure 7-58 and described in Table 7-49.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_REV | PN | DEV_REV | |||||
R-0x0 | R-0x2 | R-0x0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | TEST_REV | R | 0x0 | Test Revision |
5:2 | PN | R | 0x2 | Device Part number |
1:0 | DEV_REV | R | 0x0 | Device Revision |
REG0x80_Virtual_Control_0 is shown in Figure 7-59 and described in Table 7-50.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_RST | RESERVED | RESERVED | EN_EXTILIM | RESERVED | WD_RST | WATCHDOG | |
R/W-0x0 | R-0x0 | R-0x0 | R/W-0x1 | R-0x0 | R/W-0x0 | R/W-0x1 | |
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | REG_RST | R/W | 0x0 | Reset registers to default values and reset timer Value resets to 0 after reset completes. 0b = Not reset (default) 1b = Reset | |
6 | RESERVED | R | 0x0 | Reserved | |
5 | RESERVED | R | 0x0 | Reserved | |
4 | EN_EXTILIM | R/W | 0x1 | Reset by: REG_RESET | Enable the external ILIM_HIZ pin input current regulation
0b = Disable 1b = Enable (default) |
3 | RESERVED | R | 0x0 | Reserved | |
2 | WD_RST | R/W | 0x0 | Reset by: REG_RESET | I2C watch dog timer reset
0b = Normal (default) 1b = Reset (this bit goes back to 0 after timer reset) |
1:0 | WATCHDOG | R/W | 0x1 | Reset by: REG_RESET | Watchdog timer setting
00b = Disable 01b = 40s (default) 10b = 80s 11b = 160s |
REG0x81_Virtual_Control_1 is shown in Figure 7-60 and described in Table 7-51.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_CHG | RESERVED | FORCE_PMID_DSCHG | EN_OTG | ||||
R/W-0x1 | R-0x0 | R/W-0x0 | R/W-0x0 | ||||
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | EN_CHG | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Enable PMID pull down current source (~30mA)
0b = Charge Disable 1b = Charge Enable (default) |
6:2 | RESERVED | R | 0x0 | Reserved | |
1 | FORCE_PMID_DSCHG | R/W | 0x0 | Reset by: REG_RESET | Enable PMID pull down current source (~30mA)
0b = Disable (default) 1b = Enable |
0 | EN_OTG | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | OTG mode control
0b = OTG Disable (default) 1b = OTG Enable |