JAJSSD2A October 2023 – December 2023 BQ25638
PRODUCTION DATA
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PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADCIN | C5 | AI | External ADC Input – Connect an external analog signal up-to 1-V to monitor. |
BAT | E1 | P | Positive Terminal of Battery Pack Connection – The internal BATFET is connected between SYS and BAT. Connect a 10 µF ceramic capacitor closely to the BAT pin and GND. |
E2 | |||
E3 | |||
BATP | F1 | AI | Positive Battery Voltage Sense – Kelvin connect to positive battery terminal. Place 100 Ω series resistance between this pin and the battery positive terminal. |
BTST | B5 | P | PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap diode. Connect a 0.047 µF bootstrap capacitor from SW to BTST. |
CE | F2 | DI | Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. |
TS_BIAS | F4 | AO | Bias for the TS Resistor Voltage Divider– Provides the bias voltage for the TS resistor voltage divider. |
ILIM | F3 | AI | Input Current Limit Setting Pin – ILIM pin sets the input current limit as IINREG = KILIM / RILIM, where RILIM is connected from ILIM pin to GND. The input current is limited to the lower of the two values set by ILIM pin and IINDPM register bits. The ILIM pin can also be used to monitor input current. The input current is proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8 V). The ILIM pin function is disabled when EN_EXTILIM bit is set to 0. |
INT | F5 | DO | Open Drain Active Low Interrupt Output – Connect /INT to the logic rail via a 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to the host to report charger device status and fault. |
PG | C2 | DO | Open Drain Active Low Power Good Indicator – Connect to the pull up rail via a 2.2-kΩ resistor. LOW indicates a valid input source above PG_TH. |
PGND | A4 | P | Ground Return |
B4 | |||
C4 | |||
PMID | A2 | P | Blocking MOSFET Connection – Given the total input capacitance, place 1 µF on VBUS, and the rest on PMID, as close to the IC as possible. Typical value: 10 µF in parallel with 0.1 µF ceramic capacitor. |
B2 | |||
QON | D4 | DI | BATFET Enable or System Power Reset Control Input – If the charger is in ultra-low power mode, a logic low on this pin with tSM_EXIT duration forces the device to exit the mode. If the charger is not in ultra-low power mode, a logic low on this pin with tQON_RST initiates a full system power reset if either VVBUS < VVBUS_UVLO or BATFET_CTRL_WVBUS = 1. QON has no effect during shutdown mode. The pin contains an internal pull-up to maintain default high logic. |
REGN | A5 | P | Internal Linear Regulator Output – Internally, REGN is connected to the anode of the boot-strap diode. Connect a 10V or higher rating 4.7 µF ceramic capacitor from REGN to power ground. The capacitor should be close to the IC. The REGN LDO output is used for the internal MOSFETs gate driving voltage and for biasing the external TS pin thermistor in BQ25639. |
SCL | D5 | DI | I2C Interface Clock – Connect SCL to the logic rail through a 10 kΩ resistor. |
SDA | E5 | DIO | I2C Interface Data – Connect SDA to the logic rail through a 10 kΩ resistor. |
STAT | C1 | DO | Open Drain Charge Status Output – Indicates various charger operations. Connect to the pull up rail via a 2.2kΩ resistor. LOW indicates charging in progress. HIGH indicates charging completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz. Setting DIS_STAT = 1 will disable the STAT pin function, causing the pin to be pulled high. Leave floating if unused. |
SW | A3 | P | Switching Node Connecting to Output Inductor – Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 47 nF bootstrap capacitor from SW to BTST. |
B3 | |||
C3 | |||
SYS | D1 | P | Charger Output Voltage to System – Buck converter output connection point to the system. The internal BATFET is connected between SYS and BAT. Connect 20μF close to the SYS pin. |
D2 | |||
D3 | |||
TS | E4 | AI | Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from TS pin bias reference to TS, then to GND. Charge suspends when TS pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor. |
VBUS | A1 | P | Charger Input Voltage – The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1 uF ceramic capacitor from VBUS to GND as close as possible to IC. |
B1 |