JAJSSD2A October 2023 – December 2023 BQ25638
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
VBUS / VBAT POWER UP | ||||||
tVBUS_OVP | VBUS OVP deglitch time to set VBUS_OVP_STAT and VBUS_OVP_FLAG | 200 | µs | |||
tPOORSRC | Bad adapter detection duration | 30 | ms | |||
BATTERY CHARGER | ||||||
tTOP_OFF | Typical top-off timer accuracy | 14 | 17.5 | 21 | min | |
28 | 35 | 42 | min | |||
39 | 52 | 63 | min | |||
tSAFETY_TRKCHG | Charge safety timer accuracy in trickle charge | 1 | 1.15 | 1.3 | hr | |
tSAFETY_PRECHG | Charge safety timer accuracy in pre-charge | PRECHG_TMR = 0 | 2.1 | 2.3 | 2.6 | hr |
PRECHG_TMR = 1 | 0.53 | 0.6 | 0.65 | hr | ||
tSAFETY | Charge safety timer accuracy in fast charge | CHG_TMR = 0 | 12.5 | 14 | 15.5 | hr |
CHG_TMR = 1 | 25 | 27 | 31 | hr | ||
BATFET CONTROL | ||||||
tBATFET_DLY | Time after writing to BATFET_CTRL before BATFET turned off for ultra-low power mode or shutdown | BATFET_DLY = 1 | 12 | s | ||
BATFET_DLY = 0 | 24 | ms | ||||
tSM_EXIT | Deglitch time for QON to be pulled low in order to exit from ultra-low power mode | TSM_EXIT = 0 | 0.6 | 0.7 | 0.8 | s |
TSM_EXIT = 1 | 8.7 | 10.5 | 12.3 | ms | ||
tQON_RST | Time QON is held low to initiate system power reset | TQON_RST = 0 | 9.3 | 11 | 12.8 | s |
TQON_RST = 1 | 17.5 | 21 | 24.5 | s | ||
tBATFET_RST | Duration that BATFET is disabled during system power reset | 400 | ms | |||
I2C INTERFACE | ||||||
fSCL | SCL clock frequency | See Serial Interface section for more details | 1.0 | MHz | ||
Cb | Capacitive load for each bus line | 550 | pF | |||
DIGITAL CLOCK AND WATCHDOG | ||||||
tLP_WDT | Watchdog Reset time (EN_HIZ = 1, WATCHDOG = 160s) | 100 | 160 | s | ||
tWDT | Watchdog Reset time (EN_HIZ = 0, WATCHDOG = 160s) | 136 | 160 | s |