4 改訂履歴

Changes from * Revision (May 2017) to A Revision

• Deleted 「特長」から「補完モードでの理想的なダイオード動作」をGo
• Changed 「特長」の「薄型」を削除、「2.2µH～3.3µH」をGo
• Added 「特長」に「内蔵されたADCにより電圧、電流、電力を監視」をGo
• Added 「アプリケーション」に「脱着可能PC、タブレットPC、パワー・バンク」をGo
• Changed 「概要」の「入力電源の過負荷」を「システムの故障」にGo
• Changed アプリケーション図の「703 I2C」を「703A I2C」にGo
• Changed 18.5 V for 3-cell to 19.5 V for 3-cell and 4-cell in CELL_BATPRESZ descriptionGo
• Changed I to O for CMPOUT I/OGo
• Changed V_(IADP) to V_(IADPT) in IADPT description Go
• Deleted minimum 10-ms and added minimum to PROCHOT description Go
• Changed 10-Ω to 10-mΩ in I_{DPM_REG_ACC} in Electrical CharacteristicsGo
• Changed 10-Ω to 10-mΩ for I_{DPM_REG_ACC_ILIM} in Electrical CharacteristicsGo
• Changed REG0x07/06 to REG0x0B/0A in V_{DPM_REG_ACC} Test Conditions in Electrical CharacteristicsGo
• Changed REG0x0B/0A to REG0x07/06 in V_{OTG_REG_ACC} Test Conditions in Electrical CharacteristicsGo
• Changed REG0x01[7] = 0 to REG0x01[7] = 1 in Test Conditions for I_{BAT_BATFET_ON}Go
• Changed I_BATOVP test condition from: on SRP and SRN to: on VSYS pinGo
• Changed Q3 to ACX in CONVERTER OVER-CURRENT COMPARATOR (ACX) in Electrical CharacteristicsGo
• Added overbar to (BATDRV) in heading Go
• Added overbar to PROCHOT in Overview Go
• Changed After CHRG_OK goes HIGH to When CHRG_OK goes LOW in Input Voltage and Current Limit SetupGo
• Changed Table 1Go
• Changed 19.5 to 19.5V in 3S row SYSOVP column in Table 1Go
• Changed 0 to 0 A, lowside to low-side, and LSFET turn-on to LSFET turn-on when the HSFET is off in Continuous Conduction Mode (CCM)Go
• Changed Pulse Frequency Modulation (PFM)Go
• Changed during forward mode to during forward supplement mode in High-Accuracy Current Sense Amplifier (IADPT and IBAT)Go
• Changed REG0x33[5] to REG0x33[5](EN_PKPWR_IDPM) or REG0x33[4](EN_PKPWR_VSYS) in Two-Level Adapter Current Limit (Peak Power Mode)Go
• Added last sentence to Two-Level Adapter Current Limit (Peak Power Mode)Go
• Changed Processor Hot IndicationGo
• Changed IADP to IADPT in Figure 13Go
• Changed bq2570x to bq2570xA in Figure 14Go
• Added overbar to PROCHOT in PROCHOT StatusGo
• Changed subscript of I_{LIM2_VTH} in Input Overcurrent Protection (ACOC)Go
• Changed bq25700 to bq25703A and 3s – 18.5 V to 3s/4s – 19.5 V in System Overvoltage Protection (SYSOVP)Go
• Added REG to Battery ChargingGo
• Changed The SMBUS address is 12h (0001001_X), where X is the read/write bit. to The I2C address is D6h (1101101_X), where X is the read/write bit. in ProgrammingGo
• Added h suffix to addresses in ADDR column in Table 4Go
• Changed 0 mA – 6350 mA to 50 mA – 6400 mA for 0F/0Eh in Table 4Go
• Changed Device Address to DeviceID for 2Fh in Table 4Go
• Changed I2C address from 01h/00h to 01/00h in Figure 23Go
• Changed bit numbers from 15-8 to 7-0 in Figure 23Go
• Added <default at POR> to PWM_FREQ description in Table 5Go
• Added sentence to IBAT_GAIN description in Table 6Go
• Changed LDO to internal resistor in EN_LDO description in Table 6Go
• Changed I2C address from 31h/30h to 31/30h in ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 24Go
• Deleted Independent Comparator Reference in Table 8Go
• Changed 2.4 V and 1.3 V to 2.3 V and 1.2 V for CMP_REF in Table 8Go
• Deleted Independent Comparator Polarity in Table 8Go
• Deleted Independent Comparator Deglitch Time in Table 8Go
• Added independent to FORCE_LATCHOFF description in Table 8Go
• Changed I2C address from 33h/32h to 33/32h in ChargeOption2 Register (I2C address = 33/32h) [reset = 2B7]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 25Go
• Changed I2C address from 35h/34h to 35/34h in ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 26Go
• Added <default at POR> to BATFETOFF_ HIZ description in Table 12Go
• Added <default at POR> to PSYS_OTG_ IDCHG description in Table 12Go
• Changed I2C address from 37h/36h to 37/36h in ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]Go
• Changed bit numbers from 15-11 to 7-3, 10-9 to 2-1, 8 to 0 in Figure 27Go
• Added PROCHOT Pulse Extension Enable to EN_PROCHOT_EXT description in Table 14Go
• Changed I2C address from 39h/38h to 39/38h in ProchotOption1 Register (I2C address = 39/38h) [reset = 8120h]Go
• Changed bit numbers from 15-10 to 7-2, 9-8 to 1-0 in Figure 28Go
• Added There is a 128 mA offset. to IDCHG_VTH description in Table 15Go
• Changed 0 mA to 000000b in IDCHG_VTH description in Table 15Go
• Changed PROCHOT_PROFILE_ACOK description in Table 16Go
• Changed bit numbers from 15 to 7, 14 to 6, 13 to 5 and 12-8 to 4-0 in Figure 29Go
• Changed bit numbers from 15-8 to 7-0 in Figure 30Go
• Changed bit numbers from 15-8 to 7-0 in Figure 31Go
• Changed text in ChargeCurrent Register (I2C address = 03/02h) [reset = 0h]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 32Go
• Deleted Upon POR or when charge is disabled, the system is regulated at the MaxChargeVoltage register. from MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 33Go
• Changed bit numbers from 15-8 to 7-0 in Figure 34Go
• Deleted text and changed larger to 20-mΩ in Input Current RegistersGo
• Added paragraph to IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0F/0Eh) [reset = 4000h]Go
• Changed bit numbers from 15-8 to 7-0 in Figure 35Go
• Changed bit numbers from 15-8 to 7-0 in Figure 36Go
• Changed bit numbers from 15-8 to 7-0 in Figure 37Go
• Changed bit numbers from 15-8 to 7-0 in Figure 38Go
• Changed bit numbers from 15-8 to 7-0 in Figure 39Go
• Changed I2C address to 27/26h in ADCVBUS/PSYS Register (I2C address = 27/26h)Go
• Changed bit numbers from 15-8 to 7-0 in Figure 40Go
• Changed ADCVBUS/PSYS Register Field Descriptions into two tablesGo
• Changed I2C address to 29/28h in ADCIBAT Register (I2C address = 29/28h)Go
• Changed bit numbers from 15-8 to 7-0 in Figure 41Go
• Changed ADCIBAT Register Field Descriptions into two tablesGo
• Changed I2C address to 2B/2Ah in ADCIINCMPIN Register (I2C address = 2B/2Ah)Go
• Changed bit numbers from 15-8 to 7-0 in Figure 42Go
• Changed ADCIINCMPIN Register Field Descriptions into two tablesGo
• Changed I2C address to 2D/2Ch in ADCVSYSVBAT Register (I2C address = 2D/2Ch)Go
• Changed bit numbers from 15-8 to 7-0 in Figure 43Go
• Changed ADCVSYSVBAT Register Field Descriptions into two tablesGo
• Changed bit numbers from 15-8 to 7-0 in Figure 44Go
• Deleted 15-8, Reserved, and R from Figure 45Go
• Deleted 15-8, Reserved, and R from Table 48Go
• Changed Figure 46Go
• Changed Minimum System Voltage from 614 mV to 6144 mV in Design RequirementsGo
• Deleted Input Snubber and Filter for Voltage Spike Damping section Go
• Changed Figure 47Go
• Added Bulk input capacitors should be locate in front of input current sensing resistor. Do not recommend to put bulk input capacitors between input sensing resistor and switching MOSFET. to Input CapacitorGo
• Changed Minimum 4 - 6 pcs of 10-µF 0805 size capacitor is suggested for 45 - 65 W adapter design. to Minimum 10-µF effective capacitance (7 pcs of 10-µF 0805 size capacitor) is suggested for 45 W-65 W adapter. in Input CapacitorGo
• Changed Minimum 6 pcs of 10-µF 0805 size capacitor is suggested to be placed by the inductor. to Minimum 10-µF effective capacitance (7 pcs of 10-µF 0805 size capacitor) is suggested to be placed by the inductor, and 50-µF effective distributed capacitance on Vsys output. in Output CapacitorGo