External N-channel MOSFETs are used for a synchronous switching buck battery charger. The gate drivers are integrated into the IC with 5 V of gate drive voltage. An external gate drive voltage can be provided directly into the DRV_SUP pin for increased efficiency.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, R_DS(ON), and the gate-to-drain charge, Q_GD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as an example the power loss is a function of duty cycle (D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance (R_{DS(ON)_top}), input voltage (V_IN), switching frequency (f_S), turn-on time (t_on) and turn-off time (t_off):

• I_{L_DC} is the average inductor DC current;
• I_ripple is the inductor current ripple peak-to-peak value;

The first item P_{con_top} represents the conduction loss which is straight forward. The second term P_{sw_top} represents the multiple switching loss items in top MOSFET including voltage and current overlap losses (P_{IV_top}), MOSFET parasitic output capacitance loss (P_{Qoss_top}) and gate drive loss (P_{Gate_top}). To calculate voltage and current overlap losses (P_{IV_top}):

• t_on is the MOSFET turn-on time that V_DS falling time from V_IN to almost zero (MOSFET turn on conduction voltage);
• t_off is the MOSFET turn-off time that I_DS falling time from I_peak to zero;

The MOSFET turn-on and turn-off times are given by:

Equation 25.

where Q_sw is the switching charge, I_on is the turn-on gate driving current, and I_off is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (Q_GD) and gate-to-source charge (Q_GS):

Gate driving current can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on gate resistance (R_on), and turn-off gate resistance (R_off) of the gate driver:

Equation 27.

To calculate top MOSFET parasitic output capacitance loss (P_{Qoss_top}):

• Q_oss is the MOSFET parasitic output charge which can be found in MOSFET datasheet. It is recommended to limit the total switch node capacitance C_SW (nF) < 160/VIN; for example, for a 60-V application, it is recommended to keep the total C_SW < 2.67 nF

To calculate top MOSFET gate drive loss (P_{Gate_top}):

• Q_{Gate_top} is the top MOSFET gate charge which can be found in MOSFET datasheet;
• Note here V_IN is used instead of real gate drive voltage because the gate drive is generated based on LDO from V_IN, the total gate drive related loss are all considered when V_IN is used for gate drive loss calculation.
• Alternatively, gate drive voltage can be supplied directly by external high efficiency supply into the DRV_SUP pin. In this case, the power loss to drive the gates becomes: P_{Gate_top} =V_{DRV_SUP}· Q_{Gate_top} · f_S

The bottom-side MOSFET loss also includes conduction loss and switching loss:

The first item P_{con_bottom} represents the conduction loss which is straight forward. The second term P_{sw_bottom} represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (P_{RR_bottom}), Dead time body diode conduction loss (P_{Dead_bottom}) and gate drive loss (P_{Gate_bottom}). The detail calculation can be found below:

• Q_rr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;

• V_F is the body diode forward conduction voltage drop;
• t_{dead_rise} is the SW rising edge deadtime between top and bottom MOSFETs which is around 45 ns;
• t_{dead_fall} is the SW falling edge deadtime between top and bottom MOSFETs which is around 45 ns;

P_{Gate_bottom} can follow the same method as top MOSFET gate drive loss calculation approach.

Power-path FETs for providing power to SYS from either VAC or VBAT are selected as N-channel MOSFETs. The gate drivers are integrated into the IC with 10 V of gate drive voltage; however, the gate drive voltage can be reduced to 7 V using the PWRPATH_REDUCE_VDRV register bit if desired.