JAJSVE9 July   2024 BQ25820

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics (BQ25820)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power-On-Reset
      2. 7.3.2 Device Power-Up From Battery Without Input Source
      3. 7.3.3 Device Power Up from Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 MODE Pin Configuration
        3. 7.3.3.3 REGN Regulator (REGN LDO)
        4. 7.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 7.3.3.5 Device HIZ Mode
      4. 7.3.4 Battery Charging Management
        1. 7.3.4.1 Autonomous Charging Cycle
          1. 7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 7.3.4.2 Li-Ion Battery Charging Profile
        3. 7.3.4.3 LiFePO4 Battery Charging Profile
        4. 7.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 7.3.4.5 Charging Safety Timer
        6. 7.3.4.6 Thermistor Qualification
          1. 7.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 7.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 7.3.5 Power Path Management
        1. 7.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.5.1.1 Input Current Regulation
            1. 7.3.5.1.1.1 ILIM_HIZ Pin
          2. 7.3.5.1.2 Input Voltage Regulation
            1. 7.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 7.3.6 Reverse Mode Power Direction
      7. 7.3.7 Integrated 16-Bit ADC for Monitoring
      8. 7.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 7.3.8.1 Power Good Indicator (PG)
        2. 7.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9 Serial Interface
        1. 7.3.9.1 Data Validity
        2. 7.3.9.2 START and STOP Conditions
        3. 7.3.9.3 Byte Format
        4. 7.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.9.5 Target Address and Data Direction Bit
        6. 7.3.9.6 Single Write and Read
        7. 7.3.9.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25820 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Charge Voltage Selection
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Inductor Selection
          5. 8.2.1.2.5 Input (VAC / SYS) Capacitor
          6. 8.2.1.2.6 Output (VBAT) Capacitor
          7. 8.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 8.2.1.2.8 Power MOSFETs Selection
          9. 8.2.1.2.9 ACFETs and BATFETs Selection
        3. 8.2.1.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RRV|36
サーマルパッド・メカニカル・データ
発注情報
7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)

There are two distinct thresholds to limit the charge current (if both are enabled, the lowest limit of these will apply):

  1. ICHG pin pull down resistor (hardware control)
  2. ICHG_REG register bits (host software control)

To set the maximum charge current using the ICHG pin, a pull-down resistor to PGND is used. It is required to use a 5-mΩ RBAT_SNS sense resistor. The charge current limit is controlled by:

Equation 4. ICHG_MAX=KICHGRICHG

The precharge current limit is defined as IPRECHG_MAX = 20% x ICHG_MAX, and the termination current is ITERM = 10% x ICHG_MAX.

The actual charge current limit is the lower value between ICHG pin setting and I2C register setting (ICHG_REG). For example, if the register setting is 10 A (0xC8), and ICHG pin has a 10-kΩ resistor (KICHG = 50 A-kΩ) to ground for 5 A, the actual charge current limit is 5 A. The device regulates ICHG pin at VREF_ICHG. If ICHG pin voltage exceeds VREF_ICHG, the device enters charge current regulation.

The ICHG pin can also be used to monitor charge current when device is not in charge current regulation. When not in charge current regulation, the voltage on ICHG pin (VICHG) is proportional to the actual charging current. ICHG pin can be used to monitor battery current with the following relationship:

Equation 5. IBAT=KICHG×VICHGRICHG×VREF_ICHG

For example, if ICHG pin is set with 10-kΩ resistor, and the ICHG voltage 1.0V, the actual charge current is between 2.4 A to 2.6 A (based on KICHG specified).

If ICHG pin is shorted to PGND, the charge current limit is set by the ICHG_REG register. If hardware charge current limit function is not needed, it is recommended to short this pin to PGND. The ICHG pin function can be disabled by setting the EN_ICHG_PIN bit to 0 (recommended when pin is shorted to PGND). When the pin is disabled, charge current limit and monitoring functions via ICHG pin are not available.

To set the maximum charge current using the ICHG_REG register bits, write to the ICHG_REG register bits. The charge current limit range is from 400 mA to 20,000 mA with 50 mA/step. The default ICHG_REG is set to maximum code, allowing ICHG pin to limit the current in hardware.