SLUSFN3
July 2024
BQ25820
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics (BQ25820)
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Device Power-On-Reset
7.3.2
Device Power-Up From Battery Without Input Source
7.3.3
Device Power Up from Input Source
7.3.3.1
VAC Operating Window Programming (ACUV and ACOV)
7.3.3.2
MODE Pin Configuration
7.3.3.3
REGN Regulator (REGN LDO)
7.3.3.4
Switching Frequency and Synchronization (FSW_SYNC)
7.3.3.5
Device HIZ Mode
7.3.4
Battery Charging Management
7.3.4.1
Autonomous Charging Cycle
7.3.4.1.1
Charge Current Programming (ICHG pin and ICHG_REG)
7.3.4.2
Li-Ion Battery Charging Profile
7.3.4.3
LiFePO4 Battery Charging Profile
7.3.4.4
Charging Termination for Li-ion and LiFePO4
7.3.4.5
Charging Safety Timer
7.3.4.6
Thermistor Qualification
7.3.4.6.1
JEITA Guideline Compliance in Charge Mode
7.3.4.6.2
Cold/Hot Temperature Window in Reverse Mode
7.3.5
Power Path Management
7.3.5.1
Dynamic Power Management: Input Voltage and Input Current Regulation
7.3.5.1.1
Input Current Regulation
7.3.5.1.1.1
ILIM_HIZ Pin
7.3.5.1.2
Input Voltage Regulation
7.3.5.1.2.1
Max Power Point Tracking (MPPT) for Solar PV Panel
7.3.6
Reverse Mode Power Direction
7.3.7
Integrated 16-Bit ADC for Monitoring
7.3.8
Status Outputs (PG, STAT1, STAT2, and INT)
7.3.8.1
Power Good Indicator (PG)
7.3.8.2
Charging Status Indicator (STAT1, STAT2 Pins)
7.3.8.3
Interrupt to Host (INT)
7.3.9
Serial Interface
7.3.9.1
Data Validity
7.3.9.2
START and STOP Conditions
7.3.9.3
Byte Format
7.3.9.4
Acknowledge (ACK) and Not Acknowledge (NACK)
7.3.9.5
Target Address and Data Direction Bit
7.3.9.6
Single Write and Read
7.3.9.7
Multi-Write and Multi-Read
7.4
Device Functional Modes
7.4.1
Host Mode and Default Mode
7.4.2
Register Bit Reset
7.5
BQ25820 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Typical Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
ACUV / ACOV Input Voltage Operating Window Programming
8.2.1.2.2
Charge Voltage Selection
8.2.1.2.3
Switching Frequency Selection
8.2.1.2.4
Inductor Selection
8.2.1.2.5
Input (VAC / SYS) Capacitor
8.2.1.2.6
Output (VBAT) Capacitor
8.2.1.2.7
Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
8.2.1.2.8
Power MOSFETs Selection
8.2.1.2.9
ACFETs and BATFETs Selection
8.2.1.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RRV|36
サーマルパッド・メカニカル・データ
RRV|36
QFND780
12
Revision History
DATE
REVISION
NOTES
July 2024
*
Initial Release