JAJSH50A March   2019  – June 2019 BQ25886

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  Device Power Up from Battery without Input Source
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 Poor Source Qualification
        2. 8.3.3.2 Input Source Type Detection
          1. 8.3.3.2.1 D+/D– Detection Sets Input Current Limit
        3. 8.3.3.3 Power Up REGN Regulator (LDO)
        4. 8.3.3.4 Converter Power Up
      4. 8.3.4  Input Current Optimizer (ICO)
      5. 8.3.5  Buck Mode Operation from Battery (OTG)
      6. 8.3.6  PowerPath Management
        1. 8.3.6.1 Narrow VDC Architecture
        2. 8.3.6.2 Dynamic Power Management
        3. 8.3.6.3 Supplement Mode
      7. 8.3.7  Battery Charging Management
        1. 8.3.7.1 Autonomous Charging Cycle
        2. 8.3.7.2 Battery Charging Profile
        3. 8.3.7.3 Charging Termination
        4. 8.3.7.4 Thermistor Qualification
          1. 8.3.7.4.1 JEITA Guideline Compliance in Charge Mode
        5. 8.3.7.5 Charging Safety Timer
      8. 8.3.8  Status Outputs
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT)
      9. 8.3.9  Input Current Limit on ILIM Pin
      10. 8.3.10 Voltage and Current Monitoring
        1. 8.3.10.1 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.1.1 Input Over-Voltage Protection
          2. 8.3.10.1.2 Input Under-Voltage Protection
          3. 8.3.10.1.3 System Over-Voltage Protection
          4. 8.3.10.1.4 System Over-Current Protection
        2. 8.3.10.2 Voltage and Current Monitoring in OTG Buck Mode
          1. 8.3.10.2.1 VBUS Over-voltage Protection
          2. 8.3.10.2.2 VBUS Over-Current Protection
      11. 8.3.11 Thermal Regulation and Thermal Shutdown
        1. 8.3.11.1 Thermal Protection in Boost Mode
        2. 8.3.11.2 Thermal Protection in OTG Buck Mode
      12. 8.3.12 Battery Protection
        1. 8.3.12.1 Battery Over-Voltage Protection (BATOVP)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
        4. 9.2.2.4 ILIM resistor
        5. 9.2.2.5 ICHGSET resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Device Power-On-Reset

The internal bias circuits are powered from either VBAT or VBUS when it rises above VVBUS_UVLO_RISING or VBAT_UVLO_RISING. When VBUS rises above VVBUS_UVLO_RISING or BAT rises above VBAT_UVLO_RISING, the BATFET driver is active.