JAJSHF0B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
VBUS/BAT POWER UP | ||||||
tVBUS_OV | VBUS OVP reaction time | VBUS rising above VBUS_OV threshold to converter turn off | 200 | ns | ||
tPOORSRC | Bad adapter detection duration | 30 | ms | |||
BATTERY CHARGER | ||||||
tTERM_DGL | Deglitch time for charge termination | Charge current falling below ITERM | 250 | ms | ||
tRECGH_DGL | Deglitch time for recharge threshold | BAT voltage falling below VRECHG = 100 mV | 250 | ms | ||
tBAT_OVP_DGL | Deglitch time for battery over-voltage to disable charge | 1 | µs | |||
tTOP_OFF | Typical Top-Off Timer Accuracy | TOP_OFF_TIMER = 30 min | 24 | 30 | 36 | min |
tSAFETY | Charge Safety Timer Accuracy | CHG_TIMER = 12 hours | 10.8 | 12 | 13.2 | hr |
I2C INTERFACE | ||||||
fSCL | SCL clock frequency | 1000 | kHZ | |||
tSU_STA | Data set-up time | 10 | ns | |||
tHD_DAT | Data hold time | 0 | 70 | ns | ||
trDA | Rise time of SDA signal | 10 | 80 | ns | ||
tfDA | Fall time of SDA signal | 10 | 80 | ns | ||
DIGITAL CLOCK AND WATCHDOG TIMER | ||||||
fLPDIG | Digital low power clock | REGN LDO disabled | 18 | 30 | 45 | kHZ |
fDIG | Digital clock | REGN LDO enabled | 1.35 | 1.5 | 1.65 | MHz |
tWDT | Watchdog Reset time | WATCHDOG[1:0] = 160 s, REGN LDO disabled | 100 | 160 | sec | |
tWDT | Watchdog Reset time | WATCHDOG[1:0] = 160 s, REGN LDO enabled | 136 | 160 | sec |