JAJSFD5D March   2015  – October 2022 BQ25890 , BQ25892

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings (1)
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Device Power-On-Reset (POR)
      2. 9.2.2  Device Power Up from Battery without Input Source
      3. 9.2.3  Device Power Up from Input Source
        1. 9.2.3.1 Power Up REGN Regulation (LDO)
        2. 9.2.3.2 Poor Source Qualification
        3. 9.2.3.3 Input Source Type Detection
          1. 9.2.3.3.1 D+/D– Detection Sets Input Current Limit (BQ25890)
          2. 9.2.3.3.2 PSEL/OTG Pins Set Input Current Limit (BQ25892)
          3. 9.2.3.3.3 Force Input Current Limit Detection
        4. 9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5 Converter Power-Up
      4. 9.2.4  Input Current Optimizer (ICO)
      5. 9.2.5  Boost Mode Operation from Battery
      6. 9.2.6  Power Path Management
        1. 9.2.6.1 Narrow VDC Architecture
        2. 9.2.6.2 Dynamic Power Management
        3. 9.2.6.3 Supplement Mode
      7. 9.2.7  Battery Charging Management
        1. 9.2.7.1 Autonomous Charging Cycle
        2. 9.2.7.2 Battery Charging Profile
        3. 9.2.7.3 Charging Termination
        4. 9.2.7.4 Resistance Compensation (IRCOMP)
        5. 9.2.7.5 Thermistor Qualification
          1. 9.2.7.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6 Charging Safety Timer
      8. 9.2.8  Battery Monitor
      9. 9.2.9  Status Outputs ( PG, STAT, and INT)
        1. 9.2.9.1 Power Good Indicator ( PG)
        2. 9.2.9.2 Charging Status Indicator (STAT)
        3. 9.2.9.3 Interrupt to Host (INT)
      10. 9.2.10 BATET (Q4) Control
        1. 9.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3 BATFET Full System Reset
      11. 9.2.11 Current Pulse Control Protocol
      12. 9.2.12 Input Current Limit on ILIM
      13. 9.2.13 Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1 Thermal Protection in Buck Mode
        2. 9.2.13.2 Thermal Protection in Boost Mode
      14. 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1 Input Overvoltage (ACOV)
          2. 9.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2 Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1 VBUS Overcurrent Protection
          2. 9.2.14.2.2 Boost Mode Overvoltage Protection
      15. 9.2.15 Battery Protection
        1. 9.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2 Battery Over-Discharge Protection
        3. 9.2.15.3 System Overcurrent Protection
      16. 9.2.16 Serial Interface
        1. 9.2.16.1 Data Validity
        2. 9.2.16.2 START and STOP Conditions
        3. 9.2.16.3 Byte Format
        4. 9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5 Target Address and Data Direction Bit
        6. 9.2.16.6 Single Read and Write
        7. 9.2.16.7 Multi-Read and Multi-Write
    3. 9.3 Device Functional Modes
      1. 9.3.1 Host Mode and Default Mode
    4. 9.4 Register Maps
      1. 9.4.1  REG00
      2. 9.4.2  REG01
      3. 9.4.3  REG02
      4. 9.4.4  REG03
      5. 9.4.5  REG04
      6. 9.4.6  REG05
      7. 9.4.7  REG06
      8. 9.4.8  REG07
      9. 9.4.9  REG08
      10. 9.4.10 REG09
      11. 9.4.11 REG0A
      12. 9.4.12 REG0B
      13. 9.4.13 REG0C
      14. 9.4.14 REG0D
      15. 9.4.15 REG0E
      16. 9.4.16 REG0F
      17. 9.4.17 REG10
      18. 9.4.18 REG11
      19. 9.4.19 REG12
      20. 9.4.20 REG13
      21. 9.4.21 REG14
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Buck Input Capacitor
        3. 10.2.2.3 System Output Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 12-1) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
  2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
  4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground.
  5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
  7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the VQFN information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB Attachment Application Report.