JAJSFD5D March   2015  – October 2022 BQ25890 , BQ25892

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings (1)
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Device Power-On-Reset (POR)
      2. 9.2.2  Device Power Up from Battery without Input Source
      3. 9.2.3  Device Power Up from Input Source
        1. 9.2.3.1 Power Up REGN Regulation (LDO)
        2. 9.2.3.2 Poor Source Qualification
        3. 9.2.3.3 Input Source Type Detection
          1. 9.2.3.3.1 D+/D– Detection Sets Input Current Limit (BQ25890)
          2. 9.2.3.3.2 PSEL/OTG Pins Set Input Current Limit (BQ25892)
          3. 9.2.3.3.3 Force Input Current Limit Detection
        4. 9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5 Converter Power-Up
      4. 9.2.4  Input Current Optimizer (ICO)
      5. 9.2.5  Boost Mode Operation from Battery
      6. 9.2.6  Power Path Management
        1. 9.2.6.1 Narrow VDC Architecture
        2. 9.2.6.2 Dynamic Power Management
        3. 9.2.6.3 Supplement Mode
      7. 9.2.7  Battery Charging Management
        1. 9.2.7.1 Autonomous Charging Cycle
        2. 9.2.7.2 Battery Charging Profile
        3. 9.2.7.3 Charging Termination
        4. 9.2.7.4 Resistance Compensation (IRCOMP)
        5. 9.2.7.5 Thermistor Qualification
          1. 9.2.7.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6 Charging Safety Timer
      8. 9.2.8  Battery Monitor
      9. 9.2.9  Status Outputs ( PG, STAT, and INT)
        1. 9.2.9.1 Power Good Indicator ( PG)
        2. 9.2.9.2 Charging Status Indicator (STAT)
        3. 9.2.9.3 Interrupt to Host (INT)
      10. 9.2.10 BATET (Q4) Control
        1. 9.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3 BATFET Full System Reset
      11. 9.2.11 Current Pulse Control Protocol
      12. 9.2.12 Input Current Limit on ILIM
      13. 9.2.13 Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1 Thermal Protection in Buck Mode
        2. 9.2.13.2 Thermal Protection in Boost Mode
      14. 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1 Input Overvoltage (ACOV)
          2. 9.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2 Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1 VBUS Overcurrent Protection
          2. 9.2.14.2.2 Boost Mode Overvoltage Protection
      15. 9.2.15 Battery Protection
        1. 9.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2 Battery Over-Discharge Protection
        3. 9.2.15.3 System Overcurrent Protection
      16. 9.2.16 Serial Interface
        1. 9.2.16.1 Data Validity
        2. 9.2.16.2 START and STOP Conditions
        3. 9.2.16.3 Byte Format
        4. 9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5 Target Address and Data Direction Bit
        6. 9.2.16.6 Single Read and Write
        7. 9.2.16.7 Multi-Read and Multi-Write
    3. 9.3 Device Functional Modes
      1. 9.3.1 Host Mode and Default Mode
    4. 9.4 Register Maps
      1. 9.4.1  REG00
      2. 9.4.2  REG01
      3. 9.4.3  REG02
      4. 9.4.4  REG03
      5. 9.4.5  REG04
      6. 9.4.6  REG05
      7. 9.4.7  REG06
      8. 9.4.8  REG07
      9. 9.4.9  REG08
      10. 9.4.10 REG09
      11. 9.4.11 REG0A
      12. 9.4.12 REG0B
      13. 9.4.13 REG0C
      14. 9.4.14 REG0D
      15. 9.4.15 REG0E
      16. 9.4.16 REG0F
      17. 9.4.17 REG10
      18. 9.4.18 REG11
      19. 9.4.19 REG12
      20. 9.4.20 REG13
      21. 9.4.21 REG14
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Buck Input Capacitor
        3. 10.2.2.3 System Output Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from Revision C (May 2018) to Revision D (October 2022)

  • データシート全体にわたって WEBENCH を削除Go
  • データシート全体にわたって包括的な用語を更新Go

Changes from Revision B (May 2016) to Revision C (May 2018)

  • WEBENCH のリンクをデータシートに追加Go
  • Added "SW (peak for 10 ns duration)" To the Section 8.1 Go
  • Updated the Section 8.4 valuesGo
  • Changed VSYS TYP value From: VBAT + 50 mV To: I(SYS) + 150 mVGo
  • Changed the title of Figure 8-4 From: Charge Current Accuracy To: I2C Setting Go
  • Changed axis title of Figure 8-8 From: BAT Voltage (V) To: Input Current Limit (mA)Go
  • Changed VVREF to VREGN in Equation 2 Go
  • Changed VREF to VREGN in Figure 9-8 Go
  • Added sentence to the Battery Monitor secton "In battery only mode, .."Go
  • Changed the Description values of Table 9-27 From: mV To: mAGo
  • Changed the Type values of Bits 6 to Bit 0 in Table 9-29 From: R/W To: RGo
  • Added VREF system pullup voltage to Table 10-1 Go

Changes from Revision A (June 2015) to Revision B (May 2016)

  • 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加Go

Changes from Revision * (March 2015) to Revision A (June 2015)

  • データシートのタイトルに「テクノロジ」を追加Go
  • Deleted text form the OTG pin Description "OTG = High, IINLIM is set to USB500 mode". Go
  • Changed the Description of the OTG pin in the Pin Functions table Go
  • Changed V(SLEEP) and V(SLEEPZ) Unit From: V To: mV Go
  • Added TYP values to IIN(DPM_ACC) in the Section 8.5 table Go
  • Deleted D+/D- DETECTION (bq25890) from the Section 8.6 Go
  • Added condition "DCR = 10 mΩ" to Figure 8-1 Go
  • Deleted VCHG_REG and IBAT_REG at Q4 gate Control in the Section 9.1 Go
  • Deleted "SDP_STAT bit is updated to indicate USB100 or other input source" from Section 9.2.3.3 Go
  • Changed Figure 9-1, SDP(USB100/USB500) To: SDP (USB500) Go
  • Deleted USB SDP (USB100) and the OTG Pin column from Table 9-3 and Table 9-4 Go
  • Added text to the Section 9.2.3.3.2 section: "To implement USB100 in the system..."Go
  • Deleted section: Plug in USB100 Source Go
  • Added text to Section 9.2.3.4, "After Input Voltage Limit Threshold..." Go
  • Changed text in Section 9.2.4 From: "After DCP type..." To: "After DCP or MaxCharge type" Go
  • Changed Equation 1, From: BATCOMP, VREG + VCLAMP To: BATCOMP, VCLAMP Go
  • Changed the Description of the INLIM Bits in Table 9-9 Go
  • Changed , Bits 3 to 0, From: Default: 128mA (0011) To: Default: 256mA (0011)Go
  • Changed Bit 1 From: SDP_STAT To: Reserved Go
  • Changed VIN To: VBUS in Equation 6 Go
  • Changed Input Capacitor To: Section 10.2.2.2 Go
  • Changed ICIN to IPMID in Section 10.2.2.2 and Equation 7 Go
  • Changed "15-V input voltage. 22-μF capacitanc" To: "14-V input voltage. 8.2-μF capacitance" in Section 10.2.2.2 Go
  • Changed Output Capacitor To: Section 10.2.2.3 Go
  • Changed ICOUT To: ICSYS in Equation 8 , Changed Equation 9 Go
  • Deleted Graph "Power UP"Go