JAJSFD5D March   2015  – October 2022 BQ25890 , BQ25892

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings (1)
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Device Power-On-Reset (POR)
      2. 9.2.2  Device Power Up from Battery without Input Source
      3. 9.2.3  Device Power Up from Input Source
        1. 9.2.3.1 Power Up REGN Regulation (LDO)
        2. 9.2.3.2 Poor Source Qualification
        3. 9.2.3.3 Input Source Type Detection
          1. 9.2.3.3.1 D+/D– Detection Sets Input Current Limit (BQ25890)
          2. 9.2.3.3.2 PSEL/OTG Pins Set Input Current Limit (BQ25892)
          3. 9.2.3.3.3 Force Input Current Limit Detection
        4. 9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5 Converter Power-Up
      4. 9.2.4  Input Current Optimizer (ICO)
      5. 9.2.5  Boost Mode Operation from Battery
      6. 9.2.6  Power Path Management
        1. 9.2.6.1 Narrow VDC Architecture
        2. 9.2.6.2 Dynamic Power Management
        3. 9.2.6.3 Supplement Mode
      7. 9.2.7  Battery Charging Management
        1. 9.2.7.1 Autonomous Charging Cycle
        2. 9.2.7.2 Battery Charging Profile
        3. 9.2.7.3 Charging Termination
        4. 9.2.7.4 Resistance Compensation (IRCOMP)
        5. 9.2.7.5 Thermistor Qualification
          1. 9.2.7.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6 Charging Safety Timer
      8. 9.2.8  Battery Monitor
      9. 9.2.9  Status Outputs ( PG, STAT, and INT)
        1. 9.2.9.1 Power Good Indicator ( PG)
        2. 9.2.9.2 Charging Status Indicator (STAT)
        3. 9.2.9.3 Interrupt to Host (INT)
      10. 9.2.10 BATET (Q4) Control
        1. 9.2.10.1 BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2 BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3 BATFET Full System Reset
      11. 9.2.11 Current Pulse Control Protocol
      12. 9.2.12 Input Current Limit on ILIM
      13. 9.2.13 Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1 Thermal Protection in Buck Mode
        2. 9.2.13.2 Thermal Protection in Boost Mode
      14. 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1 Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1 Input Overvoltage (ACOV)
          2. 9.2.14.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2 Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1 VBUS Overcurrent Protection
          2. 9.2.14.2.2 Boost Mode Overvoltage Protection
      15. 9.2.15 Battery Protection
        1. 9.2.15.1 Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2 Battery Over-Discharge Protection
        3. 9.2.15.3 System Overcurrent Protection
      16. 9.2.16 Serial Interface
        1. 9.2.16.1 Data Validity
        2. 9.2.16.2 START and STOP Conditions
        3. 9.2.16.3 Byte Format
        4. 9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5 Target Address and Data Direction Bit
        6. 9.2.16.6 Single Read and Write
        7. 9.2.16.7 Multi-Read and Multi-Write
    3. 9.3 Device Functional Modes
      1. 9.3.1 Host Mode and Default Mode
    4. 9.4 Register Maps
      1. 9.4.1  REG00
      2. 9.4.2  REG01
      3. 9.4.3  REG02
      4. 9.4.4  REG03
      5. 9.4.5  REG04
      6. 9.4.6  REG05
      7. 9.4.7  REG06
      8. 9.4.8  REG07
      9. 9.4.9  REG08
      10. 9.4.10 REG09
      11. 9.4.11 REG0A
      12. 9.4.12 REG0B
      13. 9.4.13 REG0C
      14. 9.4.14 REG0D
      15. 9.4.15 REG0E
      16. 9.4.16 REG0F
      17. 9.4.17 REG10
      18. 9.4.18 REG11
      19. 9.4.19 REG12
      20. 9.4.20 REG13
      21. 9.4.21 REG14
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Buck Input Capacitor
        3. 10.2.2.3 System Output Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

GUID-99B15CD3-87C5-41CC-B930-800D839CA59F-low.gif Figure 7-1 RTW Package24-Pin WQFNTop View
GUID-B3E458AB-CB36-415E-A229-60E252092E65-low.gif Figure 7-2 RTW Package24-Pin WQFNTop View
PIN TYPE(1) DESCRIPTION
NAME BQ25890 BQ25892
VBUS 1 1 P Charger Input Voltage.
The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
D+ 2 – AIO Positive line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter.
PSEL – 2 DI Power source selection input.
High indicates a USB host source and Low indicates an adapter source.
D– 3 – AIO Negative line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter.
PG – 3 DO Open drain active low power good indicator.
Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is within VVBUS_OP, above SLEEP mode threshold (VSLEEPZ), and current limit is above IBATSRC(30 mA).
STAT 4 4 DO Open drain charge status output to indicate various charger operation.
Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz.
The STAT pin function can be disabled when STAT_DIS bit is set.
SCL 5 5 DI I2C Interface clock.
Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 6 DIO I2C Interface data.
Connect SDA to the logic rail through a 10-kΩ resistor.
INT 7 7 DO Open-drain Interrupt Output.
Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault.
OTG 8 8 DI Active high enable pin during boost mode.
The boost mode is activated when OTG_CONFIG =1 and OTG pin is high
CE 9 9 DI Active low Charge Enable pin.
Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
ILIM 10 10 AI Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current

ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = KILIM/RILIM. The actual input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500 mA is not support on ILIM pin.

ILIM pin can also be used to monitor input current when the voltage is below 0.8 V. The input current is proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8)

The ILIM pin function can be disabled when EN_ILIM bit is 0.
TS 11 11 AI Temperature qualification voltage input.
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor.
QON 12 12 DI BATFET enable/reset control input.
When BATFET is in ship mode, a logic low of tSHIPMODE (typical 1sec) duration turns on BATFET to exit shipping mode. .
When VBUS is not plugged-in, a logic low of tQON_RST (typical 15sec) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (typical 0.3sec) and then re-enable BATFET to provide full system power reset.
The pin contains an internal pull-up to maintain default high logic
BAT 13,14 13, 14 P Battery connection point to the positive terminal of the battery pack.
The internal BATFET is connected between BAT and SYS. Connect a 10 µF closely to the BAT pin.
SYS 15,16 15,16 P System connection point.
The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20 µF closely to the SYS pin.
PGND 17,18 17,18 P Power ground connection for high-current power converter node.
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
SW 19,20 19,20 P Switching node connecting to output inductor.
Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST.
BTST 21 21 P PWM high side driver positive supply.
Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 µF bootstrap capacitor from SW to BTST.
REGN 22 22 P PWM low side driver positive supply output.
Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 µF (10 V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.
PMID 23 23 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
Given the total input capacitance, put 1 µF on VBUS to PGND, and the rest capacitance on PMID to PGND.
DSEL 24 – DO Open-drain D+/D- multiplexer selection output.
Connect the DSEL to a logic rail via 10-KΩ resistor. The pin is normally float and pull-up by external resistor. During Section 9.2.3.3, the pin drives low to indicate the BQ25890 D+/D- detection is in progress and needs to take control of D+, D- signals. When detection is completed, the pin keeps low when MaxCharge™ adapter is detected. The pin returns to float and pulls high by external resistor when other input source type is detected.
NC – 24 No Connect
PowerPAD™ P Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)