JAJSEU9B September   2017  – September 2019 BQ25910

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery without Input Source
      3. 7.3.3  Device Power Up from Input Source
      4. 7.3.4  Power Up REGN LDO
      5. 7.3.5  Poor Source Qualification
      6. 7.3.6  Converter Power-Up
      7. 7.3.7  Three-Level Buck Converter Theory of Operation
      8. 7.3.8  Host Mode and Default Mode
        1. 7.3.8.1 Host Mode and Default Mode in BQ25910
      9. 7.3.9  Battery Charging Management
        1. 7.3.9.1 Autonomous Charging Cycle
      10. 7.3.10 Master Charger and Parallel Charger Interactions
      11. 7.3.11 Battery Charging Profile
        1. 7.3.11.1 Charging Termination
        2. 7.3.11.2 Differential Battery Voltage Remote Sensing
        3. 7.3.11.3 Charging Safety Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lossless Current Sensing
      2. 7.4.2 Dynamic Power Management
      3. 7.4.3 Interrupt to Host (INT)
      4. 7.4.4 Protections
        1. 7.4.4.1 Voltage and Current Monitoring
          1. 7.4.4.1.1 Input Over-Voltage (VVBUS_OV)
          2. 7.4.4.1.2 Input Under-Voltage (VPOORSRC)
          3. 7.4.4.1.3 Flying Capacitor Over- or Under-Voltage Protection (VCFLY_OVP and VCFLY_UVP)
          4. 7.4.4.1.4 Over Current Protection
        2. 7.4.4.2 Thermal Regulation and Thermal Shutdown
        3. 7.4.4.3 Battery Protection
          1. 7.4.4.3.1 Battery Over-Voltage Protection (BATOVP)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Data Validity
      3. 7.5.3 START and STOP Conditions
      4. 7.5.4 Byte Format
      5. 7.5.5 Acknowledge (ACK) and Not Acknowledge (NACK)
      6. 7.5.6 Slave Address and Data Direction Bit
      7. 7.5.7 Single Read and Write
      8. 7.5.8 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 I2C Registers
        1. 7.6.1.1  Battery Voltage Regulation Limit Register (Address = 0h) [reset = AAh]
          1. Table 5. REG00 Register Field Descriptions
        2. 7.6.1.2  Charger Current Limit Register (Address = 1h) [reset = 46h]
          1. Table 6. REG01 Register Field Descriptions
        3. 7.6.1.3  Input Voltage Limit Register (Address = 2h) [reset = 04h]
          1. Table 7. REG02 Register Field Descriptions
        4. 7.6.1.4  Input Current Limit Register (Address = 3h) [reset = 13h]
          1. Table 8. REG03 Register Field Descriptions
        5. 7.6.1.5  Reserved Register (Address = 4h) [reset = 03h]
          1. Table 9. REG04 Register Field Descriptions
        6. 7.6.1.6  Charger Control 1 Register (Address = 5h) [reset = 9Dh]
          1. Table 10. REG05 Register Field Descriptions
        7. 7.6.1.7  Charger Control 2 Register (Address = 6h) [reset = 33h]
          1. Table 11. REG06 Register Field Descriptions
        8. 7.6.1.8  INT Status Register (Address = 7h) [reset = X]
          1. Table 12. REG07 Register Field Descriptions
        9. 7.6.1.9  FAULT Status Register (Address = 8h) [reset = X]
          1. Table 13. REG08 Register Field Descriptions
        10. 7.6.1.10 INT Flag Status Register (Address = 9h) [reset = 00h]
          1. Table 14. REG09 Register Field Descriptions
        11. 7.6.1.11 FAULT Flag Register (Address = Ah) [reset = 00h]
          1. Table 15. REG0A Register Field Descriptions
        12. 7.6.1.12 INT Mask Register (Address = Bh) [reset = 00h]
          1. Table 16. REG0h Register Field Descriptions
        13. 7.6.1.13 FAULT Mask Register (Address = Ch) [reset = 00h]
          1. Table 17. REG0C Register Field Descriptions
        14. 7.6.1.14 Part Information Register (Address = Dh) [reset = 0Ah]
          1. Table 18. REG0D Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Passive Recommendation
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Flying Capacitor
        5. 8.2.2.5 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
        1. 11.1.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFF|36
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BATP, BATN, SW) VBAT = 4.5V, VBUS = 0 - 5V, SCL, SDA = 0V or 1.8V, TJ < 85°C, EN_CHG = 0 6.5 10 μA
IVBUS_HIZ Input supply current (VBUS) in HIZ VBUS = 5V, High-Z Mode, no battery 30 μA
VBUS < VVBUS_OV, High-Z Mode, no battery 50 μA
IVBUS Input supply current (VBUS) VBUS > VSLEEPZ, VBAT = 3.8V, ICHG = 0A, converter not switching 20 μA
VBUS > VSLEEPZ, VBAT = 3.8V, converter switching, IOUT = 0A 13 mA
VBUS / VBAT POWER UP
VVBUS_OP VBUS operating range 3.9 14 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.6 V
VSLEEP Enter sleep mode threshold VBUS falling, VBUS - VBAT,
VBAT = 4V, TJ = 0°C - 85°C		 15 60 110 mV
VSLEEPZ Exit sleep mode threshold VBUS rising, VBUS - VBAT,
VBAT = 4V, TJ = 0°C - 85°C		 115 220 275 mV
VVBUS_OV VBUS over-voltage rising threshold VBUS rising 14 14.3 14.7 V
VBUS over-voltage falling threshold VBUS falling 13.3 13.65 14 V
VBAT_UVLOZ Battery for active I2C, no VBUS 2.3 V
VPOORSRC Bad adapter detection threshold 3.7 V
IPOORSRC Bad adapter detection current source 20 mA
POWER-PATH
RON_QBLK (QBLK) Top reverse blocking MOSFET on-resistance between VBUS and PMID (QBLK) TJ = –40°C - 125°C 14 22 mΩ
RON_QHSA (Q1) Outer, high-side switching MOSFET on-resistance between PMID and CFLY+ (Q1) TJ = –40°C - 125°C 22 40 mΩ
RON_QHSB (Q3) Inner, high-side switching MOSFET on-resistance between CFLY+ and SW (Q3) TJ = –40°C - 125°C 12 20 mΩ
RON_QLSB (Q4) Inner, low-side switching MOSFET on-resistance between SW and CFLY- (Q4) TJ = –40°C - 125°C 8 13 mΩ
RON_QLSA (Q2) Outer, low-side switching MOSFET on-resistance between CFLY- and GND (Q2) TJ = –40°C - 125°C 8 13 mΩ
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3.5 4.775 V
VREG_STEP Typical charge voltage regulation step 5 mV
VREG_ACC Charge voltage regulation accuracy VREG = 4.2V or 4.35V or 4.4V,
TJ = –40°C - 85°C		 -0.4 0.4 %
ICHG_RANGE Typical charge current regulation range 1000 6000 mA
ICHG_STEP Typical charge current regulation step 50 mA
ICHG_ACC Charge current regulation accuracy ICHG = 2A, 3A, 4A, 5A, 6A,
TJ = –40°C - 85°C		 -10 10 %
ITERM_ACC Termination current regulation accuracy VBUS = 9V, ICHG = 4A, ITERM = 1.0A,
TJ = 0°C - 85°C		 0.9 1 1.1 A
VBAT_SHORT Short battery voltage falling threshold VBAT falling 1.85 2.00 2.15 V
VBAT_LOWV VBAT LOWV Rising threshold to start fast-charging VBAT rising, VBATLOW = 3.2V 3.1 3.2 3.3 V
VBAT LOWV Falling threshold to stop fast-charging VBAT falling, VBATLOW = 3.2V 2.9 3 3.1 V
VBAT_LOWV VBAT LOWV Rising threshold to start fast-charging VBAT rising, VBATLOW = 3.5V 3.4 3.5 3.6 V
VBAT LOWV Falling threshold to stop fast-charging VBAT falling, VBATLOW = 3.5V 3.2 3.3 3.4 V
RBATP BATP Input resistance VBAT = 4V, VBUS = 5V, EN_CHG = 0 0.6 MΩ
RBATN BATN Input resistance VBAT = 4V, VBUS = 5V, EN_CHG = 0 0.6 MΩ
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Input voltage regulation range 3.9 14 V
VINDPM_STEP Input voltage regulation step 100 mV
VINDPM_ACC Input voltage regulation accuracy VINDPM = 4.3V 4.121 4.3 4.447 V
VINDPM = 7.8V 7.566 7.8 8.034 V
VINDPM = 10.8V 10.476 10.8 11.124 V
IINDPM_RANGE Input current regulation range 500 3600 mA
IINDPM_STEP Input current regulation step 100 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA, TJ = –40°C - 85°C 410 500 mA
IINDPM = 1500mA, TJ = –40°C - 85°C 1275 1500 mA
IINDPM = 2500mA, TJ = –40°C - 85°C 2125 2500 mA
IINDPM = 3000mA, TJ = –40°C - 85°C 2540 3000 mA
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP Battery over-voltage rising threshold VBAT rising, as percentage of VREG 102 104 106 %
Battery over-voltage falling threshold VBAT falling, as percentage of VREG 100 102 103 %
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 80°C 80 °C
TREG = 120°C 120 °C
TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 120 °C
BUCK MODE OPERATION
FSW PWM switching frequency Switching-node frequency 1.35 1.5 1.65 MHz
DMAX Maximum PWM Duty Cycle 97 %
REGN LDO
VREGN REGN LDO output voltage VVBUS = 12V, IREGN = 40mA 4.85 5 V
VVBUS = 5V, IREGN = 20mA 4.7 4.8 V
IREGN REGN LDO current limit VVBUS = 5V, VREGN = 3.8V 50 mA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL Pull-up rail 1.8V 1.3 V
VIL Input low threshold level, SDA and SCL Pull-up rail 1.8V 0.4 V
VOL Output low threshold level, SDA Sink current = 5mA 0.4 V
IBIAS High level leakage current, SDA and SCL Pull-up rail 1.8V 1 μA
LOGIC OUTPUT PIN (/INT)
VOL Output low threshold level Sink current = 5mA 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8V 1 μA