JAJSEU9B September   2017  – September 2019 BQ25910

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery without Input Source
      3. 7.3.3  Device Power Up from Input Source
      4. 7.3.4  Power Up REGN LDO
      5. 7.3.5  Poor Source Qualification
      6. 7.3.6  Converter Power-Up
      7. 7.3.7  Three-Level Buck Converter Theory of Operation
      8. 7.3.8  Host Mode and Default Mode
        1. 7.3.8.1 Host Mode and Default Mode in BQ25910
      9. 7.3.9  Battery Charging Management
        1. 7.3.9.1 Autonomous Charging Cycle
      10. 7.3.10 Master Charger and Parallel Charger Interactions
      11. 7.3.11 Battery Charging Profile
        1. 7.3.11.1 Charging Termination
        2. 7.3.11.2 Differential Battery Voltage Remote Sensing
        3. 7.3.11.3 Charging Safety Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lossless Current Sensing
      2. 7.4.2 Dynamic Power Management
      3. 7.4.3 Interrupt to Host (INT)
      4. 7.4.4 Protections
        1. 7.4.4.1 Voltage and Current Monitoring
          1. 7.4.4.1.1 Input Over-Voltage (VVBUS_OV)
          2. 7.4.4.1.2 Input Under-Voltage (VPOORSRC)
          3. 7.4.4.1.3 Flying Capacitor Over- or Under-Voltage Protection (VCFLY_OVP and VCFLY_UVP)
          4. 7.4.4.1.4 Over Current Protection
        2. 7.4.4.2 Thermal Regulation and Thermal Shutdown
        3. 7.4.4.3 Battery Protection
          1. 7.4.4.3.1 Battery Over-Voltage Protection (BATOVP)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Data Validity
      3. 7.5.3 START and STOP Conditions
      4. 7.5.4 Byte Format
      5. 7.5.5 Acknowledge (ACK) and Not Acknowledge (NACK)
      6. 7.5.6 Slave Address and Data Direction Bit
      7. 7.5.7 Single Read and Write
      8. 7.5.8 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 I2C Registers
        1. 7.6.1.1  Battery Voltage Regulation Limit Register (Address = 0h) [reset = AAh]
          1. Table 5. REG00 Register Field Descriptions
        2. 7.6.1.2  Charger Current Limit Register (Address = 1h) [reset = 46h]
          1. Table 6. REG01 Register Field Descriptions
        3. 7.6.1.3  Input Voltage Limit Register (Address = 2h) [reset = 04h]
          1. Table 7. REG02 Register Field Descriptions
        4. 7.6.1.4  Input Current Limit Register (Address = 3h) [reset = 13h]
          1. Table 8. REG03 Register Field Descriptions
        5. 7.6.1.5  Reserved Register (Address = 4h) [reset = 03h]
          1. Table 9. REG04 Register Field Descriptions
        6. 7.6.1.6  Charger Control 1 Register (Address = 5h) [reset = 9Dh]
          1. Table 10. REG05 Register Field Descriptions
        7. 7.6.1.7  Charger Control 2 Register (Address = 6h) [reset = 33h]
          1. Table 11. REG06 Register Field Descriptions
        8. 7.6.1.8  INT Status Register (Address = 7h) [reset = X]
          1. Table 12. REG07 Register Field Descriptions
        9. 7.6.1.9  FAULT Status Register (Address = 8h) [reset = X]
          1. Table 13. REG08 Register Field Descriptions
        10. 7.6.1.10 INT Flag Status Register (Address = 9h) [reset = 00h]
          1. Table 14. REG09 Register Field Descriptions
        11. 7.6.1.11 FAULT Flag Register (Address = Ah) [reset = 00h]
          1. Table 15. REG0A Register Field Descriptions
        12. 7.6.1.12 INT Mask Register (Address = Bh) [reset = 00h]
          1. Table 16. REG0h Register Field Descriptions
        13. 7.6.1.13 FAULT Mask Register (Address = Ch) [reset = 00h]
          1. Table 17. REG0C Register Field Descriptions
        14. 7.6.1.14 Part Information Register (Address = Dh) [reset = 0Ah]
          1. Table 18. REG0D Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Passive Recommendation
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Flying Capacitor
        5. 8.2.2.5 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
        1. 11.1.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFF|36
サーマルパッド・メカニカル・データ
発注情報

7.4.4.2 Thermal Regulation and Thermal Shutdown

The device monitors internal junction temperature TJ to avoid overheating the chip and limits the device surface temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits), the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers. Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit goes high, and an INT is asserted to the host.

Additionally, the device has thermal shutdown to turn off the converter when device surface temperature exceeds TSHUT. The fault register TSHUT_STAT is set and an INT pulse is asserted to the host. The converter turns back on when device temperature is below TSHUT_HYS.