JAJSL52A april 2020 – february 2021 BQ25968
PRODUCTION DATA
The device requires a cap between the CDRVH and CDRVL_ADDRMS pins to operate correctly. The CDRVL_ADDRMS pin also allows setting the default I2C address and power-up AC_OVP threshold for external OVP FET control. Pull to GND with a resistor for the desired setting shown in Table 9-2. Once I2C communication begins with the device, the register sets the AC_OVP threshold.
RESISTOR VALUE TO GND ON CDRVL_ADDRMS | I2C ADDR (NVM_I2CADDR_ALT = 0) | I2C ADDR (NVM_I2CADDR_ALT = 1) | AC_OVP SETTING | MASTER, SLAVE, OR STANDALONE OPERATION |
---|---|---|---|---|
18 KΩ | 0×65 | 0×66 | 6.5 V | Master |
39 KΩ | 0×66 | 0×67 | (Disabled) | Slave |
75 KΩ | 0×65 | 0×67 | 11 V | Standalone |
Open (>150 KΩ) | 0×66 | 0×67 | 6.5 V | Standalone |
If a standalone device is needed with the AC_OVP function disabled, use the BQ25971.