JAJSL52A april 2020 – february 2021 BQ25968
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENTS | ||||||
IQ_VBUS | VBUS Operating Quiescent Current | ADC Disabled, Charge Disabled, OVPGATE not used | 285 | µA | ||
ADC Disabled, Charge Disabled, OVPGATE used | 345 | µA | ||||
ADC Enabled (fastest mode), Charge Disabled | 400 | µA | ||||
ADC Enabled (slowest mode), Charge Disabled | 385 | µA | ||||
IQ_BAT | Battery Only Quiescent Current | ADC Disabled, Charge Disabled, VIN Not Present | 8 | 18 | µA | |
ADC Enabled (slowest mode), Charge Disabled, VBUS Not Present | 385 | µA | ||||
ADC Enabled (fastest mode), Charge Disabled, VBUS Not Present | 385 | µA | ||||
RESISTANCES | ||||||
RQB_ON | VBUS to PMID On Resistance | VBUS = 9 V | 6 | 8 | mΩ | |
RQCH1_ON | On resistance of QCH1 | VPMID = 9 V | 22 | 27 | mΩ | |
RQDH1_ON | On resistance of QDH1 | CFLY = 4.5 V | 10 | 16 | mΩ | |
RQCL1_ON | On resistance of QCL1 | VOUT = 4.5 V | 7 | 14 | mΩ | |
RQDL1_ON | On resistance of QDL1 | CFLY = 4.5 V | 8 | 14 | mΩ | |
RQCH2_ON | On resistance of QCH2 | VPMID = 9 V | 22 | 27 | mΩ | |
RQDH2_ON | On resistance of QDH2 | CFLY = 4.5 V | 10 | 16 | mΩ | |
RQCL2_ON | On resistance of QCL2 | VOUT = 4.5 V | 7 | 14 | mΩ | |
RQDL2_ON | On resistance of QDL2 | CFLY = 4.5 V | 8 | 14 | mΩ | |
RVBUS_PD | VBUS pull-down resistance | 6 | kΩ | |||
RVAC_PD | VAC pull-down resistance | 130 | Ω | |||
INTERNAL THRESHOLDS | ||||||
VBUSUVLO | Rising | VBUS Rising | 3.3 | V | ||
VACUVLO | Rising | VAC Rising | 3.3 | V | ||
Falling Hysteresis | 300 | mV | ||||
VOVPGATE | External FET Gate Drive Voltage, Measured from Gate to Source, with minimum 8 nF CGS | VAC = 8 V | 10 | V | ||
VOUTUVLO | Rising | 2.3 | V | |||
Falling Hysteresis | 100 | mV | ||||
VACPRESENT | Rising | 3.5 | V | |||
Falling Hysteresis | 300 | mV | ||||
VBUSPRESENT | Rising | 2.85 | V | |||
Falling Hysteresis | 500 | mV | ||||
VOUTPRESENT | Rising | 2.3 | 2.85 | V | ||
Falling Hysteresis | 100 | mV | ||||
TSHUT | Rising Internal (TJ) Shutdown | 150 | °C | |||
Falling Hysteresis | 30 | °C | ||||
PROTECTION and ALARMS THRESHOLD AND ACCURACY | ||||||
VOUTOVP | VOUT OVP rising threshold | 4.8 | 4.9 | 5 | V | |
VDROP | VDROP rising threshold | Adjustable in Register 0x05h, bit 4 = 0 | 300 | mV | ||
VDROP | VDROP rising threshold | Adjustable in Register 0x05h, bit 4 = 1 | 400 | mV | ||
VBATOVP | VBAT Over-Voltage Range | Adjustable in Register 0x00h | 4.2 | 4.65 | V | |
VBAT Over-Voltage Step Size | 10 | mV | ||||
VBAT Over-Voltage Accuracy | –1% | 1% | ||||
VBAT_ALM | VBAT Alarm Range | Adjustable in Register 0x01h | 4.2 | 4.65 | V | |
VBAT Alarm Step Size | 25 | mV | ||||
VBAT Alarm Hysteresis | Falling | 50 | mV | |||
VBAT Alarm Comparator Accuracy | From VBAT = 3.5 V to 4.4 V | –0.4% | 0.4% | |||
IBAT_OCP | IBAT_OCP Range | Adjustable in Register 0x02h | 0 | 10 | A | |
IBAT_OCP Step Size | 50 | mA | ||||
IBAT_OCP Comparator Accuracy | IBAT = 6 A | –5% | 5% | |||
IBATOCP_ALM | IBATOCP_ALM Range | Adjustable in Register 0x03h | 0 | 10 | A | |
IBATOCP_ALM Step Size | 50 | mA | ||||
IBATOCP_ALM Hysteresis | Falling | 50 | mA | |||
IBATOCP_ALM Comparator Accuracy | IBAT = 6 A and 9 A | –1% | 1% | |||
IBATUCP_ALM | IBATUCP_ALM Range | Adjustable in Register 0x04h | 0 | 10 | A | |
IBATUCP_ALM Step Size | 50 | mA | ||||
IBAT_UCP_ALM Hysteresis | Rising | 50 | mA | |||
IBATUCP_ALM Comparator Accuracy | IBAT = 3 A | –2% | 2% | |||
VVAC_OVP | VAC_OVP Range | Adjustable in Register 0x05h | 6.5 | 17 | V | |
VAC_OVP Step Size | Step size valid for 11 V through 17 V only | 1 | V | |||
VAC_OVP Comparator Accuracy | Accuracy for 6.5 V | –2% | 2% | |||
VAC_OVP Comparator Accuracy | Accuracy for 11 V through 17 V | –2% | 2% | |||
VBUS_OVP | VBUS_OVP Range | Adjustable in Register 0x06h, 250 mV typical hysteresis | 6 | 12.35 | V | |
VBUS_OVP Step Size | 50 | mV | ||||
VBUS_OVP Comparator Accuracy | VBUS = 10 V | –1% | 1% | |||
VBUSOVP_ALM | VBUSOVP_ALM Range | Adjustable in Register 0x07h | 6 | 12.35 | mV | |
VBUSOVP_ALM Step Size | 50 | mV | ||||
VBUSOVP_ALM Hysteresis | Falling | 50 | mV | |||
VBUSOVP_ALM Comparator Accuracy | –0.5% | 0.5% | ||||
IBUS_OCP | IBUS_OCP Range | Adjustable in Register 0x08h | 0 | 4.75 | A | |
IBUS_OCP Step Size | 50 | mA | ||||
IBUS_OCP Comparator Accuracy | 3 A | –5% | 5% | |||
IBUS_UCP | IBUS_UCP Rising, IBAT must reach this value before the SS timeout or Switching Stops, Protection disabled until IBUS Current Reaches this Value | Adjustable in Register 0x2Bh, bit 2 = 0 | 300 | 375 | mA | |
IBUS_UCP | IBUS_UCP Rising, IBAT must reach this value before the SS timeout or Switching Stops, Protection disabled until IBUS Current Reaches this Value | Adjustable in Register 0x2Bh, bit 2 = 1 | 500 | 575 | mA | |
IBUS_UCP | IBUS_UCP Falling, Switching stops when IBUS current reaches this value | Adjustable in Register 0x2Bh, bit 2 = 0 | 10 | 150 | mA | |
IBUS_UCP Falling, Switching stops when IBUS current reaches this value | Adjustable in Register 0x2Bh, bit 2 = 1 | 100 | 250 | mA | ||
IBUSOCP_ALM | IBUSOCP_ALM Range | Adjustable in Register 0x09h | 0 | 4.95 | A | |
IBUSOCP_ALM Step Size | 50 | mA | ||||
IBUSOCP_ALM Hysteresis | Falling | 50 | mA | |||
IBUSOCP_ALM Comparator Accuracy | IBUS = 3 A (0°C to 85°C) | –4% | 4% | |||
TSBAT_FLT TSBUS_FLT | TSBUS and TSBAT voltage range | 0% | 75% | |||
TSBUS and TSBAT Threshold Step Size | 0% | 0.1953% | ||||
TSBUS and TSBAT Comparator Accuracy | –1% | 1% | ||||
TSBUS and TSBAT Falling Hysteresis | 4% | |||||
TIMINGS | ||||||
fSW | Switching Frequency | Register set to 500 kHz in Register 0x0Bh | 500 | kHz | ||
tVAC_OVP | VAC OVP reaction time | 0.1 | µs | |||
tVOUT_OVP | VAC OVP reaction time | 5.5 | µs | |||
tVAC_PD | VAC Pulldown duration | 400 | ms | |||
tVBUS_OVP | VBUS OVP reaction time (Note: The deglitch time is increased during regulation) | Not in regulation | 1 | µs | ||
tIBUS_OCP | IBUS OCP reaction time (Note: The deglitch time is increased during regulation) | Not in regulation | 75 | µs | ||
tIBUS_UCP | IBUS UCP falling reaction time (Note: The deglitch time is increased during regulation) | Not in regulation. Adjustable in Register 0x2Eh, bit 4 = 0 | 10 | µs | ||
tIBUS_UCP | IBUS UCP falling reaction time (Note: The deglitch time is increased during regulation) | Not in regulation. Adjustable in Register 0x2Eh, bit 4 = 1 | 10 | ms | ||
tVDROP | VDROP rising threshold deglitch (Note: The deglitch time is increased during regulation) | Not in regulation. Adjustable in Register 0x2Eh, bit 3 = 0 | 10 | µs | ||
tVDROP | VDROP rising threshold deglitch (Note: The deglitch time is increased during regulation) | Not in regulation. Adjustable in Register 0x2Eh, bit 3 = 1 | 5 | ms | ||
tVBAT_OVP | VBAT OVP reaction time | 0 | µs | |||
Deglitch during regulation | 5 | ms | ||||
tVOUT_OVP | VOUT OVP reaction time | 4 | µs | |||
tIBAT_OCP | IBAT OCP reaction time | 500 | µs | |||
Deglitch during regulation | 5 | ms | ||||
tINT | Duration that INT is pulled low when an event occurs | 256 | µs | |||
tREG_TIMEOUT | If the part is in regulation, but below VDROP_OVP for this amount of time, the part will stop switching. | 650 | ms | |||
tINT_REG_DGL | Deglitch when INT is pulled low after an event occurs | Rising | 100 | ms | ||
Falling | 5 | ms | ||||
TALM_DEBOUNCE | Time between consecutive faults for ALM indication | 120 | ms | |||
tBUS_DETACH | IBUS threshold reaction time | 1 | µs | |||
ADC MEASUREMENT ACCURACY AND PERFORMANCE | ||||||
tADC_CONV | Conversion Time, Each Measurement | ADC_SAMPLE[1:0] = 00 | 24 | ms | ||
ADC_SAMPLE[1:0] = 01 | 12 | |||||
ADC_SAMPLE[1:0] = 10 | 6 | |||||
ADC_SAMPLE[1:0] = 11 | 3 | |||||
ADCRES | Effective Resolution (0°C to 85°C) | ADC_SAMPLE[1:0] = 00 | 14 | bits | ||
ADC_SAMPLE[1:0] = 01 | 13 | |||||
ADC_SAMPLE[1:0] = 10 | 12 | |||||
ADC_SAMPLE[1:0] = 11 | 11 | |||||
ADC MEASUREMENT RANGES AND LSB | ||||||
IBUS_ADC | ADC Bus Current Readable in Registers 0x16h and 0x17h | Range | 0 | 5 | A | |
LSB | 1 | mA | ||||
IBUS_ADC | ADC Accuracy | 1.5 A (0°C to 85°C) | –5% | 5% | ||
IBUS_ADC | ADC Accuracy | 3 A (0°C to 85°C) | –5% | 5% | ||
VBUS_ADC | ADC Bus Voltage Readable in Registers 0x18h and 0x19h | Range | 0 | 14 | V | |
LSB | 1 | mV | ||||
VBUS_ADC | ADC Bus Voltage | Accuracy for 8V, ADC_RATE = 00 | –0.%5 | 0.5% | ||
VAC_ADC | ADC VAC Voltage Readable in Registers 0x1Ah and 0x1Bh | Range | 0 | 14 | V | |
LSB | 1 | mV | ||||
VAC_ADC | ADC VAC Voltage | Accuracy for 8 V, ADC_RATE = 00 | –0.5% | 0.5% | ||
VOUT_ADC | ADC Output Voltage Readable in Registers 0x1Ch and 0x1Dh | Range | 0 | 5 | V | |
LSB | 1 | mV | ||||
VOUT_ADC | ADC Output Voltage | Accuracy for 4 V, ADC_RATE = 00 | –0.5% | 0.5% | ||
VBAT_ADC | ADC Battery Voltage Readable in Registers 0x1Eh and 0x1Fh | Range | 0 | 5 | V | |
LSB | 1 | mV | ||||
VBAT_ADC | ADC Battery Voltage | Accuracy for 3.5 V through 4.4 V, ADC_RATE = 00 | –0.4% | 0.2% | ||
IBAT_ADC | ADC Battery Current Readable in Registers 0x20h and 0x21h | Range | 0 | 10 | A | |
LSB with 2 mΩ RSENSE | 1 | mA | ||||
IBAT_ADC | ADC Battery Current | 3 A | –2% | 2% | ||
IBAT_ADC | ADC Battery Current | 6 A | –1.5% | 1.5% | ||
IBAT_ADC | ADC Battery Current | 9 A | –1.5% | 1.5% | ||
TSBUS_ADC | ADC TSBUS pin voltage | Range | 0.2 | 2.7 | V | |
TSBUS_ADC | ADC TSBUS % of VOUT Readable in Registers 0x22h and 0x23h | Range | 0% | 50% | ||
LSB | 0.09766% | |||||
TSBUS_ADC | ADC TSBUS Accuracy | TSBUS pin voltage 2 V | –1% | 1% | ||
TSBAT_ADC | ADC TSBAT pin voltage | Range | 0.2 | 2.7 | V | |
TSBAT_ADC | ADC TSBAT pin voltage Readable in Registers 0x24h and 0x25h | Range | 0% | 50% | ||
LSB | 0.09766% | |||||
TSBAT_ADC | ADC TSBAT pin voltage | TSBAT pin voltage 2 V | –1% | 1% | ||
TDIE_ADC | ADC Die Temperature Readable in Registers 0x26h and 0x27h | Range | –40 | 150 | °C | |
LSB | 0.5 | °C | ||||
TDIE_ADC | ADC Die Temperature (Typ over temp) | ±4 | °C | |||
REGN LDO | ||||||
VREGN | REGN LDO Output Voltage | VBUS = 8 V | 5 | V | ||
IREGN | REGN LDO Current Limit | VBUS = 8 V, VREGN = 4.5 V | 50 | mA | ||
LOGIC I/O THRESHOLDS ( INT, BATP_SYNCIN) | ||||||
VIL | Input Low Threshold | ISINK = 5 mA | 0.4 | V | ||
VIH | Input High Threshold | ISINK = 5 mA | 1.3 | V | ||
ILEAK | High Level Leakage Current | VPULL-UP = 3.3 V | 1 | µA | ||
LOGIC I/O THRESHOLDS (TSBAT_SYNCOUT) | ||||||
VOH | Output High Threshold | VPULL-UP = 1.8V | 1.3 | |||
VOL | Output Low Threshold | VPULL-UP = 1.8V | 0.4 | |||
I2C LEVELS and TIMINGS | ||||||
VIL | Input Low Threshold | VPULL-UP = 1.8 V, SDA and SCL | 0.4 | V | ||
VIH | Input High Threshold | VPULL-UP = 1.8 V, SDA and SCL | 1.3 | V | ||
VOL | Output Low Threshold | IOL = 20 mA | 0.4 | V | ||
IBIAS | High Level Leakage Current | VPULL-UP = 1.8 V, SDA and SCL | 1 | µA | ||
fSCL | SCL Clock Frequency | 1 | MHz | |||
tSU_STA | Data Set-Up Time | 10 | ns | |||
tHD_DAT | Data Hold Time | 0 | 70 | ns | ||
trDA | Rise Time of SDA Signal | Cbus = 100 pF max | 10 | 80 | ns | |
tfDA | Fall Time of SDA Signal | Cbus = 100 pF max | 10 | 80 | ns |