JAJSL52 データシート

Table 9-4 can be accesses using I²C using the address programmed by the CDRVH_ADDRMS pin, and the value can be found in Table 9-2.

Table 9-4 CUSTOMER Registers

ADDRESS	ACRONYM	REGISTER NAME	SECTION
0h	BAT_OVP	Battery Voltage Limit	Go
1h	BAT_OVP_ALM	Battery Voltage Alarm	Go
2h	BAT_OCP	Charge Current Limit	Go
3h	BAT_OCP_ALM	Charge Current Alarm	Go
4h	BAT_UCP_ALM	Charge Under Current Alarm	Go
5h	AC_PROTECTION	Input Voltage Limit	Go
6h	BUS_OVP	Bus Over Voltage Protection	Go
7h	BUS_OVP_ALM	Input Voltage Alarm	Go
8h	BUS_OCP_UCP	Input Current Limit	Go
9h	BUS_OCP_ALM	Input Current Alarm	Go
Ah	CONVERTER_STATE	Converter State	Go
Bh	CONTROL	Control Register	Go
Ch	CHRG_CTRL	Charger Control 1	Go
Dh	INT_STAT	INT STAT	Go
Eh	INT_FLAG	INT Flag	Go
Fh	INT_MASK	INT Mask	Go
10h	FLT_STAT	FAULT STAT	Go
11h	FLT_FLAG	FAULT FLAG	Go
12h	FLT_MASK	FAULT MASK	Go
13h	PART_INFO	Part Information	Go
14h	ADC_CTRL	ADC Control	Go
15h	ADC_FN_DIS	ADC Function Disable	Go
16h	IBUS_ADC1	ADC BUS Current Measurement	Go
17h	IBUS_ADC0	ADC BUS Current Measurement	Go
18h	VBUS_ADC1	ADC BUS Voltage Measurement	Go
19h	VBUS_ADC0	ADC BUS Voltage Measurement	Go
1Ah	VAC_ADC1	ADC VAC Voltage Measurement	Go
1Bh	VAC_ADC0	ADC VAC Voltage Measurement	Go
1Ch	VOUT_ADC1	ADC OUT Voltage Measurement	Go
1Dh	VOUT_ADC0	ADC OUT Voltage Measurement	Go
1Eh	VBAT_ADC1	ADC BAT Voltage Measurement	Go
1Fh	VBAT_ADC0	ADC BAT Voltage Measurement	Go
20h	IBAT_ADC1	ADC BAT Current Measurement	Go
21h	IBAT_ADC0	ADC BAT Current Measurement	Go
22h	TSBUS_ADC1	ADC TSBUS Pin Voltage Measurement	Go
23h	TSBUS_ADC0	ADC TSBUS Pin Voltage Measurement	Go
24h	TSBAT_ADC1	ADC TSBAT Pin Voltage Measurement	Go
25h	TSBAT_ADC0	ADC TSBAT Pin Voltage Measurement	Go
26h	TDIE_ADC1	ADC Die Temperature Measurement	Go
27h	TDIE_ADC0	ADC Die Temperature Measurement	Go
28h	TSBUS_FLT1	TSBUS Pin Voltage Fault Setting	Go
29h	TSBAT_FLT0	TSBAT Pin Voltage Fault Setting	Go
2Ah	TDIE_ALM	Die Temp Fault Setting	Go
2Bh	CHG_CTRL	Charger Control	Go
2Ch	VOUT_OVP_STAT	VOUT_OVP status	Go
2Dh	VOUT_OVP_FLAG_MASK	VOUT_OVP FLAG and MASK	Go
2Eh	DEGLITCH	Deglitch Settings	Go

Complex bit access types are encoded to fit into small table cells. Table 9-5 shows the codes that are used for access types in this section.

Table 9-5 CUSTOMER Access Type Codes

ACCESS TYPE	CODE	DESCRIPTION
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value x may be 0 or 1

9.6.1.1 BAT_OVP Register (Address = 0h) [reset = 22h]

BAT_OVP is shown in Figure 9-13 and described in Table 9-6.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-13 BAT_OVP Register

7	6	5	4	3	2	1	0
BAT_OVP_DIS	RESERVED	BAT_OVP[5]	BAT_OVP[4]	BAT_OVP[3]	BAT_OVP[2]	BAT_OVP[1]	BAT_OVP[0]
R/W-0h	0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-0h

Table 9-6 BAT_OVP Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_DIS	R/W	0h	Y	N	N/A	Disable BAT_OVP
6	RESERVED		0h
5	BAT_OVP[5]	R/W	1h	Y	N	800 mV	Battery Overvoltage Protection Setting. When the battery voltage goes above the programmed threshold, and INT is sent, the output is disabled and CHG_EN is set to 0. The host controller should monitor the battery voltage to ensure that the adapter keeps the voltage under this threshold for proper operation. The setting is determined by BAT_OVP = 3.475 V + BAT_OVP[5:0]*25 mV Default: 4.35 V (b 10 0010)
4	BAT_OVP[4]	R/W	0h	Y	N	400 mV
3	BAT_OVP[3]	R/W	0h	Y	N	200 mV
2	BAT_OVP[2]	R/W	0h	Y	N	100 mV
1	BAT_OVP[1]	R/W	1h	Y	N	50 mV
0	BAT_OVP[0]	R/W	0h	Y	N	25 mV

9.6.1.2 BAT_OVP_ALM Register (Address = 1h) [reset = 1Ch]

BAT_OVP_ALM is shown in Figure 9-14 and described in Table 9-7.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-14 BAT_OVP_ALM Register

7	6	5	4	3	2	1	0
BAT_OVP_ALM_DIS	RESERVED	BAT_OVP_ALM[5]	BAT_OVP_ALM[4]	BAT_OVP_ALM[3]	BAT_OVP_ALM[2]	BAT_OVP_ALM[1]	BAT_OVP_ALM[0]
R/W-0h	0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-0h

Table 9-7 BAT_OVP_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_ALM_DIS	R/W	0h	Y	N	N/A	Disable BAT_OVP_ALM
6	RESERVED		0h
5	BAT_OVP_ALM[5]	R/W	0h	Y	N	800 mV	Battery Overvoltage Alarm Setting. When the battery voltage goes above the programmed threshold an INT is sent. The BAT_OVP_ALM should be set lower than BAT_OVP and the host controller should monitor the battery voltage to ensure that the adapter keeps the voltage under the BAT_OVP threshold for proper operation. The setting is determined by BAT_OVP_ALM = 3.5 V + BAT_OVP_ALM[5:0]*25 mV Default: 4.2 V (b01 1100)
4	BAT_OVP_ALM[4]	R/W	1h	Y	N	400 mV
3	BAT_OVP_ALM[3]	R/W	1h	Y	N	200 mV
2	BAT_OVP_ALM[2]	R/W	1h	Y	N	100 mV
1	BAT_OVP_ALM[1]	R/W	0h	Y	N	50 mV
0	BAT_OVP_ALM[0]	R/W	0h	Y	N	25 mV

9.6.1.3 BAT_OCP Register (Address = 2h) [reset = 3Dh]

BAT_OCP is shown in Figure 9-15 and described in Table 9-8.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-15 BAT_OCP Register

7	6	5	4	3	2	1	0
BAT_OCP_DIS	BAT_OCP[6]	BAT_OCP[5]	BAT_OCP[4]	BAT_OCP[3]	BAT_OCP[2]	BAT_OCP[1]	BAT_OCP[0]
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-1h

Table 9-8 BAT_OCP Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OCP_DIS	R/W	0h	Y	N	N/A	Disable BAT_OCP
6	BAT_OCP[6]	R/W	0h	Y	N	6400 mA	Battery Overcurrent Protection Setting. Any setting over 10 A is set to 10 A. When the battery current goes above the programmed threshold, the output is disabled. The host controller should monitor the battery current to ensure that the adapter keeps the current under this threshold for proper operation. The setting is determined by BAT_OCP = 2 A + BAT_OCP[6:0]*100 mA Default: 8.1 A (b 011 1101)
5	BAT_OCP[5]	R/W	1h	Y	N	3200 mA
4	BAT_OCP[4]	R/W	1h	Y	N	1600 mA
3	BAT_OCP[3]	R/W	1h	Y	N	800 mA
2	BAT_OCP[2]	R/W	1h	Y	N	400 mA
1	BAT_OCP[1]	R/W	0h	Y	N	200 mA
0	BAT_OCP[0]	R/W	1h	Y	N	100 mA

9.6.1.4 BAT_OCP_ALM Register (Address = 3h) [reset = 3Ch]

BAT_OCP_ALM is shown in Figure 9-16 and described in Table 9-9.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-16 BAT_OCP_ALM Register

7	6	5	4	3	2	1	0
BAT_OCP_ALM_DIS	BAT_OCP_ALM[6]	BAT_OCP_ALM[5]	BAT_OCP_ALM[4]	BAT_OCP_ALM[3]	BAT_OCP_ALM[2]	BAT_OCP_ALM[1]	BAT_OCP_ALM[0]
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-0h

Table 9-9 BAT_OCP_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OCP_ALM_DIS	R/W	0h	Y	N	N/A	Disable BAT_OCP_ALM
6	BAT_OCP_ALM[6]	R/W	0h	Y	N	6400 mA	Battery Overcurrent Alarm Setting. When the battery current goes above the programmed threshold an INT is sent. The BAT_OCP_ALM should be set lower than the BAT_OCP and the host controller should monitor the battery current to ensure that the adapter keeps the current under the BAT_OCP threshold for proper operation. The setting is determined by BAT_OCP_ALM = 2 A + BAT_OCP_ALM[6:0]*100 mA Default: 8 A
5	BAT_OCP_ALM[5]	R/W	1h	Y	N	3200 mA
4	BAT_OCP_ALM[4]	R/W	1h	Y	N	1600 mA
3	BAT_OCP_ALM[3]	R/W	1h	Y	N	800 mA
2	BAT_OCP_ALM[2]	R/W	1h	Y	N	400 mA
1	BAT_OCP_ALM[1]	R/W	0h	Y	N	200 mA
0	BAT_OVP_ALM[0]	R/W	0h	Y	N	100 mA

9.6.1.5 BAT_UCP_ALM Register (Address = 4h) [reset = 28h]

BAT_UCP_ALM is shown in Figure 9-17 and described in Table 9-10.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-17 BAT_UCP_ALM Register

7	6	5	4	3	2	1	0
BAT_UCP_ALM_DIS	BAT_UCP_ALM[6]	BAT_UCP_ALM[5]	BAT_UCP_ALM[4]	BAT_UCP_ALM[3]	BAT_UCP_ALM[2]	BAT_UCP_ALM[1]	BAT_UCP_ALM[0]
R/W-0h	R/W-0h	R/W-1h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 9-10 BAT_UCP_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_UCP_ALM_DIS	R/W	0h	Y	N	N/A	Disable BAT_UCP_ALM
6	BAT_UCP_ALM[6]	R/W	0h	Y	N	3200 mA	Battery Undercurrent Alarm Setting. When the battery current falls below the programmed threshold, an INT is sent. The host controller should monitor the battery current to determine when to disable the BQ25968 and hand overcharging to the switching charger. The setting is determined by BAT_UCP_ALM = BAT_UCP_ALM[7:0]*50 mA Default: 2 A (b0101000)
5	BAT_UCP_ALM[5]	R/W	1h	Y	N	1600 mA
4	BAT_UCP_ALM[4]	R/W	0h	Y	N	800 mA
3	BAT_UCP_ALM[3]	R/W	1h	Y	N	400 mA
2	BAT_UCP_ALM[2]	R/W	0h	Y	N	200 mA
1	BAT_UCP_ALM[1]	R/W	0h	Y	N	100 mA
0	BAT_UCP_ALM[0]	R/W	0h	Y	N	50 mA

9.6.1.6 AC_PROTECTION Register (Address = 5h) [reset = 3h]

AC_PROTECTION is shown in Figure 9-18 and described in Table 9-11.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-18 AC_PROTECTION Register

7	6	5	4	3	2	1	0
AC_OVP_STAT	AC_OVP_FLAG	AC_OVP_MASK	RESERVED		AC_OVP[2]	AC_OVP[1]	AC_OVP[0]
R-0h	R-0h	R/W-0h	R-x		R/W-0h	R/W-1h	R/W-1h

Table 9-11 AC_PROTECTION Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	AC_OVP_STAT	R	0h	Y	N/A	N/A	Status of AC_OVP. Persists until condition is no longer valid.
6	AC_OVP_FLAG	R	0h	Y	N/A	N/A	Set when an AC_OVP event occurs. Cleared upon read.
5	AC_OVP_MASK	R/W	0h	Y	N	N/A	Masks an AC_OVP event from sending an INT.
4-3	RESERVED	R	x	N	N	N/A	RESERVED
2	AC_OVP[2]	R/W	0h	Y	N	4 V	Bus Overvoltage Protection Setting. When the bus voltage reaches the programmed threshold, OVPGATE turns off the OVP FET. The host controller should monitor the bus voltage to ensure that the adapter keeps the voltage under this threshold for proper operation. The setting is determined by AC_OVP = 11 V + AC_OVP[3:0]*1 V Writing all 1s to these bits sets the AC_OVP to 6.5 V
1	AC_OVP[1]	R/W	1h	Y	N	2 V
0	AC_OVP[0]	R/W	1h	Y	N	1 V

9.6.1.7 BUS_OVP Register (Address = 6h) [reset = 3Ah]

BUS_OVP is shown in Figure 9-19 and described in Table 9-12.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-19 BUS_OVP Register

7	6	5	4	3	2	1	0
VBUS_PD_EN	BUS_OVP[6]	BUS_OVP[5]	BUS_OVP[4]	BUS_OVP[3]	BUS_OVP[2]	BUS_OVP[1]	BUS_OVP[0]
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-1h	R/W-0h

Table 9-12 BUS_OVP Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	VBUS_PD_EN	R/W	0h	Y	N	N/A	0: Pulldown disabled, 1: Pulldown enabled Enabling this will turn off the external OVPFET, and conduct current from VBUS to GND through an internal diode. Any time the OVPFET charge pump is not running, this pulldown device will be active to help discharge VBUS after a hot-plug event.
6	BUS_OVP[6]	R/W	0h	Y	N	3200 mV	Bus Overvoltage Setting. When the bus voltage reaches the programmed threshold, QB is turned off and CH_EN is set to 0. The host controller should monitor the bus voltage to ensure that the adapter keeps the voltage under the BUS_OVP threshold for proper operation. The setting is determined by BUS_OVP = 5.95 V + BUS_OVP[6:0]*50 mV Default: 8.9 V (b011 1010)
5	BUS_OVP[5]	R/W	1h	Y	N	1600 mV
4	BUS_OVP[4]	R/W	1h	Y	N	800 mV
3	BUS_OVP[3]	R/W	1h	Y	N	400 mV
2	BUS_OVP[2]	R/W	0h	Y	N	200 mV
1	BUS_OVP[1]	R/W	1h	Y	N	100 mV
0	BUS_OVP[0]	R/W	0h	Y	N	50 mV

9.6.1.8 BUS_OVP_ALM Register (Address = 7h) [reset = 38h]

BUS_OVP_ALM is shown in Figure 9-20 and described in Table 9-13.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-20 BUS_OVP_ALM Register

7	6	5	4	3	2	1	0
BUS_OVP_ALM_DIS	BUS_OVP_ALM[6]	BUS_OVP_ALM[5]	BUS_OVP_ALM[4]	BUS_OVP_ALM[3]	BUS_OVP_ALM[2]	BUS_OVP_ALM[1]	BUS_OVP_ALM[0]
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 9-13 BUS_OVP_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BUS_OVP_ALM_DIS	R/W	0h	Y	N	N/A	Disable BUS_OVP_ALM
6	BUS_OVP_ALM[6]	R/W	0h	Y	N	3200 mV	Bus Overvoltage Alarm Setting. When the bus voltage reaches the programmed threshold, an INT is sent. The host controller should monitor the bus voltage to ensure that the adapter keeps the voltage under the BUS_OVP threshold for proper operation. The setting is determined by BUS_OVP_ALM = 6 V + BUS_OVP_ALM[6:0]*50 mV Default: 8.8 V (b011 1000)
5	BUS_OVP_ALM[5]	R/W	1h	Y	N	1600 mV
4	BUS_OVP_ALM[4]	R/W	1h	Y	N	800 mV
3	BUS_OVP_ALM[3]	R/W	1h	Y	N	400 mV
2	BUS_OVP_ALM[2]	R/W	0h	Y	N	200 mV
1	BUS_OVP_ALM[1]	R/W	0h	Y	N	100 mV
0	BUS_OVP_ALM[0]	R/W	0h	Y	N	50 mV

9.6.1.9 BUS_OCP_UCP Register (Address = 8h) [reset = Dh]

BUS_OCP_UCP is shown in Figure 9-21 and described in Table 9-14.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-21 BUS_OCP_UCP Register

7	6	5	4	3	2	1	0
BUS_OCP_DIS	IBUS_UCP_RISE_FLAG	IBUS_UCP_RISE_MASK	IBUS_UCP_FALL_FLAG	BUS_OCP[3]	BUS_OCP[2]	BUS_OCP[1]	BUS_OCP[0]
R/W-0h	R-0h	R/W-0h	R-0h	R/W-1h	R/W-1h	R/W-0h	R/W-1h

Table 9-14 BUS_OCP_UCP Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BUS_OCP_DIS	R/W	0h	Y	N	N/A	BUS_OCP Disable
6	IBUS_UCP_RISE_FLAG	R	0h	Y	N/A	N/A	Bus Undercurrent Threshold Rising Flag. An INT is sent when this occurs, and is cleared upon read.
5	IBUS_UCP_RISE_MASK	R/W	0h	Y	N	N/A	Bus Undercurrent Threshold Rising INT Mask. 0: Not Masked, 1: Masked
4	IBUS_UCP_FALL_FLAG	R	0h	Y	N/A	N/A	Bus Undercurrent Threshold Falling Flag. An INT is sent when this occurs, and is cleared upon read.
3	BUS_OCP[3]	R/W	1h	Y	N	2 A	Bus Overcurrent Protection Setting. When the bus current reaches the programmed threshold, the output is disabled. The host controller should monitor the bus current to ensure that the adapter keeps the current under this threshold for proper operation. The setting is determined by BUS_OCP = 1 A + BUS_OCP[6:0]*250 mA Default: 4.25 A (b1101)
2	BUS_OCP[2]	R/W	1h	Y	N	1 A
1	BUS_OCP[1]	R/W	0h	Y	N	500 mA
0	BUS_OCP[0]	R/W	1h	Y	N	250 mA

9.6.1.10 BUS_OCP_ALM Register (Address = 9h) [reset = 50h]

BUS_OCP_ALM is shown in Figure 9-22 and described in Table 9-15.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-22 BUS_OCP_ALM Register

7	6	5	4	3	2	1	0
BUS_OCP_ALM_DIS	BUS_OCP_ALM[6]	BUS_OCP_ALM[5]	BUS_OCP_ALM[4]	BUS_OCP_ALM[3]	BUS_OCP_ALM[2]	BUS_OCP_ALM[1]	BUS_OCP_ALM[0]
R/W-0h	R/W-1h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 9-15 BUS_OCP_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	BUS_OCP_ALM_DIS	R/W	0h	Y	N	N/A	BUS_OCP_ALM Disable
6	BUS_OCP_ALM[6]	R/W	1h	Y	N	3200 mA	Bus Overcurrent Alarm Setting. When the bus current reaches the programmed threshold, an INT is sent. The host controller should monitor the bus current to ensure that the adapter keeps the current under BUS_OCP for proper operation. The setting is determined by BUS_OCP_ALM = BUS_OCP_ALM[6:0]*50 mA - 50 mA Writing all 0s is 0 A Default: 4 A (b1010000)
5	BUS_OCP_ALM[5]	R/W	0h	Y	N	1600 mA
4	BUS_OCP_ALM[4]	R/W	1h	Y	N	800 mA
3	BUS_OCP_ALM[3]	R/W	0h	Y	N	400 mA
2	BUS_OCP_ALM[2]	R/W	0h	Y	N	200 mA
1	BUS_OCP_ALM[1]	R/W	0h	Y	N	100 mA
0	BUS_OCP_ALM[0]	R/W	0h	Y	N	50 mA

9.6.1.11 CONVERTER_STATE Register (Address = Ah) [reset = 0h]

CONVERTER_STATE is shown in Figure 9-23 and described in Table 9-16.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-23 CONVERTER_STATE Register

7	6	5	4	3	2	1	0
TSHUT_FLAG	TSHUT_STAT	VBUS_ ERRORLO_ STAT	VBUS_ ERRORHI_ STAT	SS_TIMEOUT_FLAG	CONV_SWITCHING_STAT	CONV_OCP_ FLAG	FLYCAP_ SHORT_FLAG
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 9-16 CONVERTER_STATE Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	TSHUT_FLAG	R	0h	Y	N/A	N/A	Thermal Shutdown Flag. An INT is sent when this event happens, and is cleared when read.
6	TSHUT_STAT	R	0h	Y	N/A	N/A	Thermal Shutdown Status. This register is 1 until the event no longer persists.
5	VBUS_ERRORLO_STAT	R	0h	Y	N/A	N/A	VBUS is too low for the converter to start switching. This bit shows the current status, and is 0 only when the event is not happening.
4	VBUS_ERRORHI_STAT	R	0h	Y	N/A	N/A	VBUS is too high for the converter to start switching. This bit shows the current status, and is 0 only when the event is not happening.
3	SS_TIMEOUT_FLAG	R	0h	N	N/A	N/A	Soft-Start Timeout Flag. If the current is not ramped to the proper level in SS_TIMEOUT_SET[1:0] time, the converter will stop switching. An INT is sent when this event happens, and is cleared when read.
2	CONV_SWITCHING_STAT	R	0h	N	N/A	N/A	An interrupt is sent when the converter starts switching and the SS timer starts. The adapter current must be ramped to the IBUS_UCP_RISE threshold SS_TIMEOUT or switching will stop. This bit is not maskable. Only one INT is set when switching starts. The bit can be read at any time to determine if the part is switching or not.
1	CONV_OCP_FLAG	R	0h	N	N/A	N/A	Converter Overcurrent Flag. When any internal switching FET reaches current limit, an INT is sent when this event happens, and is cleared when read.
0	PIN_DIAG_FAIL_FLAG	R	0h	Y	N/A	N/A	Pin Diagnostic Fail Flag. When CHG_EN is set to '1', several fault conditions are checked on the CFLY and VOUT pins to ensure proper operation. If a diagnostic fails, an INT is sent when this event happens, and is cleared when read.

9.6.1.12 CONTROL Register (Address = Bh) [reset = 40h]

CONTROL is shown in Figure 9-24 and described in Table 9-17.

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All bits are RESET BY REG_RST.

Figure 9-24 CONTROL Register

7	6	5	4	3	2	1	0
REG_RST	FSW_SET[2:0]			WD_TIMEOUT_FLAG	WATCHDOG_DIS	WATCHDOG[1:0]
R/W-0h	R/W-4h			R-0h	R/W-0h	R/W-0h

Table 9-17 CONTROL Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	REG_RST	R/W	0h	Y	N	N/A	0 = No Register Reset 1 = Reset Registers to their Default Values Always reads 0
6	FSW_SET[2]	R/W	1h	N	N	N/A	Set the Switching Frequency 000: Slowest (187.5 kHz) 001: 250 kHz 010: 300 kHz 011: 375 kHz 100: 500 kHz (default) 101-111: Fastest (750 kHz) If master or slave, max frequency is 500 kHz
5	FSW_SET[1]	R/W	0h	N	N	N/A
4	FSW_SET[0]	R/W	0h	N	N	N/A
3	WD_TIMEOUT_FLAG	R	0h	Y	N/A	N/A	Watchdog Timeout Flag. An INT is sent when this event happens, and is cleared when read.
2	WATCHDOG_DIS	R/W	0h	Y	N	N/A	0 = Watchdog Enabled 1 = Watchdog Disabled
1	WATCHDOG[1]	R/W	0h	Y	N	N/A	Watchdog Timing, (Cleared by any completed read or write I²C transaction) 00 = 0.5 s (default) 01 = 1 s 10 = 5 s 11 = 30 s
0	WATCHDOG[0]	R/W	0h	Y	N	N/A

9.6.1.13 CHRG_CTRL Register (Address = Ch) [reset = 0h]

CHRG_CTRL is shown in Figure 9-25 and described in Table 9-18.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-25 CHRG_CTRL Register

7	6	5	4	3	2	1	0
CHG_EN	MS[1:0]		FREQ_SHIFT[1:0]		TSBUS_DIS	TSBAT_DIS	TDIE_DIS
R/W-0h	R-0h		R/W-0h		R/W-0h	R/W-0h	R/W-0h

Table 9-18 CHRG_CTRL Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by Reg_RST	Reset by WATCHDOG	Bit Value	Description
7	CHG_EN	R/W	0h	Y	Y	N/A	0 = Charge disabled 1 = Charge enabled
6-5	MS[1:0]	R	0h	Y	N/A	N/A	Master, Slave, or Standalone Operation. 00 = Standalone 01 = Slave 1X = Master
4-3	FREQ_SHIFT[1:0]	R/W	0h	Y	N	N/A	Adjust Fsw for EMI. 00 = Nominal Frequency 01 = +10% 10 = –10% 11 = Spread Spectrum varies frequency ±10%
2	TSBUS_DIS	R/W	0h	Y	N	N/A	Disable TSBUS protection function. 0 = Enabled 1 = Disable
1	TSBAT_DIS	R/W	0h	Y	N	N/A	Disable TSBAT protection function. 0 = Enabled 1 = Disable
0	TDIE_DIS	R/W	0h	Y	N	N/A	Disable TDIE protection function.

9.6.1.14 INT_STAT Register (Address = Dh) [reset = xh]

INT_STAT is shown in Figure 9-26 and described in Table 9-19.

Return to Summary Table.

Shows current status. All bits are RESET BY REG_RST.

Figure 9-26 INT_STAT Register

7	6	5	4	3	2	1	0
BAT_OVP_ ALM_STAT	BAT_OCP_ ALM_STAT	BUS_OVP_ ALM_STAT	BUS_OCP_ ALM_STAT	BAT_UCP_ ALM_STAT	ADAPTER_ INSERT_STAT	VBAT_INSERT_STAT	ADC_DONE_ STAT
R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x

Table 9-19 INT_STAT Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset By WATCHDOG	Bit Value	Description
7	BAT_OVP_ALM_STAT	R	x	N	N/A	N/A	BAT_OVP_ALM threshold is exceeded.
6	BAT_OCP_ALM_STAT	R	x	N	N/A	N/A	BAT_OCP_ALM threshold is exceeded.
5	BUS_OVP_ALM_STAT	R	x	N	N/A	N/A	BUS_OVP_ALM threshold is exceeded.
4	BUS_OCP_ALM_STAT	R	x	N	N/A	N/A	BUS_OCP_ALM threshold is exceeded.
3	BAT_UCP_ALM_STAT	R	x	N	N/A	N/A	BAT_UCP_ALM is below the threshold.
2	ADAPTER_INSERT_STAT	R	x	N	N/A	N/A	BUS voltage is present and above the VBUS UVLO threshold.
1	VBAT_INSERT_STAT	R	x	N	N/A	N/A	BAT voltage is present.
0	ADC_DONE_STAT	R	x	N	N/A	N/A	Indicates if the ADC conversion is complete for the requested parameters in 1-Shot Mode only. This bit will change to '0' when an ADC conversion is requested in 1-Shot Mode, and it will change back to '1' when the conversion is complete. During continuous conversion mode, this bit will be 0. 0 = Conversion not complete 1 = Conversion complete

9.6.1.15 INT_FLAG Register (Address = Eh) [reset = xh]

INT_FLAG is shown in Figure 9-27 and described in Table 9-20.

Return to Summary Table.

Only clears upon read. All bits are RESET BY REG_RST.

Figure 9-27 INT_FLAG Register

7	6	5	4	3	2	1	0
BAT_OVP_ ALM_FLAG	BAT_OCP_ ALM_FLAG	BUS_OVP_ ALM_FLAG	BUS_OCP_ ALM_FLAG	BAT_UCP_ ALM_FLAG	ADAPTER_ INSERT_FLAG	VBAT_INSERT_FLAG	ADC_DONE_ FLAG
R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x

Table 9-20 INT_FLAG Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_ALM_FLAG	R	x	N	N/A	N/A	BAT_OVP_ALM threshold has been exceeded.
6	BAT_OCP_ALM_FLAG	R	x	N	N/A	N/A	BAT_OCP_ALM threshold has been exceeded.
5	BUS_OVP_ALM_FLAG	R	x	N	N/A	N/A	BUS_OVP_ALM threshold has been exceeded.
4	BUS_OCP_ALM_FLAG	R	x	N	N/A	N/A	BUS_OCP_ALM threshold has been exceeded.
3	BAT_UCP_ALM_FLAG	R	x	N	N/A	N/A	BAT_UCP_ALM has fallen below the threshold.
2	ADAPTER_INSERT_FLAG	R	x	N	N/A	N/A	BUS voltage has been present and above the VBUS UVLO threshold.
1	VBAT_INSERT_FLAG	R	x	N	N/A	N/A	BAT votlage has been present.
0	ADC_DONE_FLAG	R	x	N	N/A	N/A	0 = Conversion not complete 1 = Conversion complete

9.6.1.16 INT_MASK Register (Address = Fh) [reset = 0h]

INT_MASK is shown in Figure 9-28 and described in Table 9-21.

Return to Summary Table.

INT will not assert low if enabled. All bits are RESET BY REG_RST.

Figure 9-28 INT_MASK Register

7	6	5	4	3	2	1	0
BAT_OVP_ ALM_MASK	BAT_OCP_ ALM_MASK	BUS_OVP_ ALM_MASK	BUS_OCP_ ALM_MASK	BAT_UCP_ ALM_MASK	ADAPTER_ INSERT_MASK	VBAT_INSERT_MASK	ADC_DONE_ MASK
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 9-21 INT_MASK Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_ALM_MASK	R/W	0h	Y	N	N/A	Masks BAT Overvoltage Alarm Event. 0 = Not Masked 1 = Masked
6	BAT_OCP_ALM_MASK	R/W	0h	Y	N	N/A	Masks BAT Overcurrent Alarm Event. 0 = Not Masked 1 = Masked
5	BUS_OVP_ALM_MASK	R/W	0h	Y	N	N/A	Masks BUS Overvoltage Alarm Event. 0 = Not Masked 1 = Masked
4	BUS_OCP_ALM_MASK	R/W	0h	Y	N	N/A	Masks BUS Overcurrent Alarm Event. 0 = Not Masked 1 = Masked
3	BAT_UCP_ALM_MASK	R/W	0h	Y	N	N/A	Masks BAT_UCP Alarm Event. 0 = Not Masked 1 = Masked
2	ADAPTER_INSERT_MASK	R/W	0h	Y	N	N/A	Masks a ADAPTER_INSERT Event. 0 = Not Masked 1 = Masked
1	VBAT_INSERT_MASK	R/W	0h	Y	N	N/A	Masks a VBAT INSERT EVENT. 0 = Not Masked 1 = Masked
0	ADC_DONE_MASK	R/W	0h	Y	N	N/A	Masks a ADC DONE Event. 0 = Not Masked 1 = Masked

9.6.1.17 FLT_STAT Register (Address = 10h) [reset = xh]

FLT_STAT is shown in Figure 9-29 and described in Table 9-22.

Return to Summary Table.

Shows current status. All bits are RESET BY REG_RST.

Figure 9-29 FLT_STAT Register

7	6	5	4	3	2	1	0
BAT_OVP_FLT_STAT	BAT_OCP_FLT_STAT	BUS_OVP_FLT_STAT	BUS_OCP_FLT_STAT	TSBUS_TSBAT_ALM_STAT	TSBAT_FLT_STAT	TSBUS_FLT_STAT	TDIE_ALM_STAT
R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x

Table 9-22 FLT_STAT Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_FLT_STAT	R	x	N	N/A	N/A	Indicates a BAT Overvoltage Event is occurring.
6	BAT_OCP_FLT_STAT	R	x	N	N/A	N/A	Indicates a BAT Overcurrent Event is occurring.
5	BUS_OVP_FLT_STAT	R	x	N	N/A	N/A	Indicates a BUS Overvoltage Event is occurring.
4	BUS_OCP_FLT_STAT	R	x	N	N/A	N/A	Indicates a BUS Overcurrent Event is occurring.
3	TSBUS_TSBAT_ALM_STAT	R	x	N	N/A	N/A	Indicates that the TSBUS or TSBAT threshold is within 5% of the TSBUS_FLT or TSBAT_FLT set threshold.
2	TSBAT_FLT_STAT	R	x	N	N/A	N/A	Indicates a BAT Over Temp Fault has Occurred TSBAT voltage falls below TSBAT_FLT setting.
1	TSBUS_FLT_STAT	R	x	N	N/A	N/A	Indicates a BUS Over Temp Fault has Occurred TSBUS votlage falls below TSBUS_FLT setting.
0	TDIE_ALM_STAT	R	x	N	N/A	N/A	Indicates a DIE Over Temp Fault has Occurred TDIE_ALM temp has been exceeded.

9.6.1.18 FLT_FLAG Register (Address = 11h) [reset = xh]

FLT_FLAG is shown in Figure 9-30 and described in Table 9-23.

Return to Summary Table.

Only clears upon read. All bits are RESET BY REG_RST.

Figure 9-30 FLT_FLAG Register

7	6	5	4	3	2	1	0
BAT_OVP_FLT_FLAG	BAT_OCP_FLT_FLAG	BUS_OVP_FLT_FLAG	BUS_OCP_FLT_FLAG	TSBUS_TSBAT_ALM_FLAG	TSBAT_FLT_FLAG	TSBUS_FLT_FLAG	TDIE_ALM_FLAG
R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x

Table 9-23 FLT_FLAG Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BAT Overvoltage Event has occurred.
6	BAT_OCP_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BAT Overcurrent Event has occurred.
5	BUS_OVP_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BUS Overvoltage Event has occurred.
4	BUS_OCP_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BUS Overcurrent Event has occurred.
3	TSBUS_TSBAT_ALM_FLAG	R	x	N	N/A	N/A	Indicates that the TSBUS or TSBAT threshold has been within 5% of the TSBUS_FLT or TSBAT_FLT set threshold.
2	TSBAT_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BAT Temp Fault has Occurred.
1	TSBUS_FLT_FLAG	R	x	N	N/A	N/A	Indicates a BUS Temp Fault has Occurred.
0	TDIE_ALM_FLAG	R	x	N	N/A	N/A	Indicates a DIE Temp Fault has Occurred.

9.6.1.19 FLT_MASK Register (Address = 12h) [reset = 0h]

FLT_MASK is shown in Figure 9-31 and described in Table 9-24.

Return to Summary Table.

INT will not assert if enabled. All bits are RESET BY REG_RST.

Figure 9-31 FLT_MASK Register

7	6	5	4	3	2	1	0
BAT_OVP_FLT_MASK	BAT_OCP_FLT_MASK	BUS_OVP_FLT_MASK	BUS_OCP_FLT_MASK	TSBUS_TSBAT_ALM_MASK	TSBAT_FLT_MASK	TSBUS_FLT_MASK	TDIE_ALM_MASK
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 9-24 FLT_MASK Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	BAT_OVP_FLT_MASK	R/W	0h	Y	N	N/A	Masks BAT Overvoltage Event. 0 = Not Masked 1 = Masked
6	BAT_OCP_FLT_MASK	R/W	0h	Y	N	N/A	Masks BAT Overcurrent Event. 0 = Not Masked 1 = Masked
5	BUS_OVP_FLT_MASK	R/W	0h	Y	N	N/A	Masks BUS Overvoltage Event. 0 = Not Masked 1 = Masked
4	BUS_OCP_FLT_MASK	R/W	0h	Y	N	N/A	Masks BUS Overcurrent Event. 0 = Not Masked 1 = Masked
3	TSBUS_TSBAT_ALM_MASK	R/W	0h	Y	N	N/A	Masks TSBUS_TSBAT_ALM Event. 0 = Not Masked 1 = Masked
2	TSBAT_FLT_MASK	R/W	0h	Y	N	N/A	Masks a BAT Temp Fault. 0 = Not Masked 1 = Masked
1	TSBUS_FLT_MASK	R/W	0h	Y	N	N/A	Masks a BUS Temp Fault. 0 = Not Masked 1 = Masked
0	TDIE_ALM_MASK	R/W	0h	Y	N	N/A	Masks a DIE Temp Fault. 0 = Not Masked 1 = Masked

9.6.1.20 PART_INFO Register (Address = 13h) [reset = xh]

PART_INFO is shown in Figure 9-32 and described in Table 9-25.

Return to Summary Table.

Figure 9-32 PART_INFO Register

7	6	5	4	3	2	1	0
RESERVED[7:4]				DEVICE_ID[3:0]
R-x				R-x

Table 9-25 PART_INFO Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset By WATCHDOG	Bit Value	Description
7	RESERVED		0
6	RESERVED		0
5	RESERVED		0
4	RESERVED		1
3	DEVICE_ID[3]	R	x	x	N/A	x	Device ID 0000 = BQ25970 0001= BQ25971 0110= BQ25968
2	DEVICE_ID[2]	R	x	x	N/A	x
1	DEVICE_ID[1]	R	x	x	N/A	x
0	DEVICE_ID[0]	R	x	x	N/A	x

9.6.1.21 ADC_CTRL Register (Address = 14h) [reset = xh]

ADC_CTRL is shown in Figure 9-33 and described in Table 9-26.

Return to Summary Table.

Bits 7-3 and bit 0 are RESET BY REG_RST.

Figure 9-33 ADC_CTRL Register

7	6	5	4	3	2	1	0
ADC_EN	ADC_RATE	ADC_AVG	ADC_AVG_INIT	ADC_SAMPLE[1:0]		RESERVED	IBUS_ADC_DIS
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h		0	R/W-0h

Table 9-26 ADC_CTRL Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset By WATCHDOG	Bit Value	Description
7	ADC_EN	R/W	0h	Y	Y	N/A	Enable ADC 0 = Disabled 1 = Enabled
6	ADC_RATE	R/W	0h	Y	N	N/A	0 = Continuous Conversion 1 = One-shot
5	ADC_AVG	R/W	0h	Y	N	N/A	0 = Single Value 1 = Running Average
4	ADC_AVG_INIT	R/W	0h	Y	N	N/A	0 = Start averaging using the existing register value 1 = Start averaging using a new ADC conversion
3-2	ADC_SAMPLE[1:0]	R/W	0h	Y	N	N/A	Sample speed of the ADC. 00 = 15-bit effective resolution 01 = 14-bit effective resolution 10 = 13-bit effective resolution 11 = 12-bit effective resolution
1	RESERVED		0
0	IBUS_ADC_DIS	R/W	0h	Y	N	N/A	0 = Enable Conversion 1 = Disable Conversion

9.6.1.22 ADC_FN_DISABLE Register (Address = 15h) [reset = 0h]

ADC_FN_DIS is shown in Figure 9-34 and described in Table 9-27.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-34 ADC_FN_DISABLE Register

7	6	5	4	3	2	1	0
VBUS_ADC_DIS	VAC_ADC_DIS	VOUT_ADC_DIS	VBAT_ADC_DIS	IBAT_ADC_DIS	TSBUS_ADC_DIS	TSBAT_ADC_DIS	TDIE_ADC_DIS
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 9-27 ADC_FN_DISABLE Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset By WATCHDOG	Bit Value	Description
7	VBUS_ADC_DIS	R/W	0h	Y	N	N/A	0 = Enable Conversion 1 = Disable Conversion
6	VAC_ADC_DIS	R/W	0h	Y	N	N/A
5	VOUT_ADC_DIS	R/W	0h	Y	N	N/A
4	VBAT_ADC_DIS	R/W	0h	Y	N	N/A
3	IBAT_ADC_DIS	R/W	0h	Y	N	N/A
2	TSBUS_ADC_DIS	R/W	0h	Y	N	N/A
1	TSBAT_ADC_DIS	R/W	0h	Y	N	N/A
0	TDIE_ADC_DIS	R/W	0h	Y	N	N/A

9.6.1.23 IBUS_ADC1 Register (Address = 16h) [reset = xh]

IBUS_ADC1 is shown in Figure 9-35 and described in Table 9-28.

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All bits are RESET BY REG_RST.

Figure 9-35 IBUS_ADC1 Register

7	6	5	4	3	2	1	0
IBUS_POL	IBUS_ADC[14:8]
R-x	R-x

Table 9-28 IBUS_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset By WATCHDOG	Bit Value	Description
7	IBUS_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	IBUS_ADC[14]	R	x	Y	N/A	16384 mA	Current of IBUS
5	IBUS_ADC[13]	R	x	Y	N/A	8192 mA
4	IBUS_ADC[12]	R	x	Y	N/A	4096 mA
3	IBUS_ADC[11]	R	x	Y	N/A	2048 mA
2	IBUS_ADC[10]	R	x	Y	N/A	1024 mA
1	IBUS_ADC[9]	R	x	Y	N/A	512 mA
0	IBUS_ADC[8]	R	x	Y	N/A	256 mA

9.6.1.24 IBUS_ADC0 Register (Address = 17h) [reset = xh]

IBUS_ADC0 is shown in Figure 9-36 and described in Table 9-29.

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All bits are RESET BY REG_RST.

Figure 9-36 IBUS_ADC0 Register

7	6	5	4	3	2	1	0
IBUS_ADC[7:0]
R-x

Table 9-29 IBUS_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset By WATCHDOG	Bit Value
7	IBUS_ADC[7]	R	x	Y	N/A	128 mA
6	IBUS_ADC[6]	R	x	Y	N/A	64 mA
5	IBUS_ADC[5]	R	x	Y	N/A	32 mA
4	IBUS_ADC[4]	R	x	Y	N/A	16 mA
3	IBUS_ADC[3]	R	x	Y	N/A	8 mA
2	IBUS_ADC[2]	R	x	Y	N/A	4 mA
1	IBUS_ADC[1]	R	x	Y	N/A	2 mA
0	IBUS_ADC[0]	R	x	Y	N/A	1 mA

9.6.1.25 VBUS_ADC1 Register (Address = 18h) [reset = xh]

VBUS_ADC1 is shown in Figure 9-37 and described in Table 9-30.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-37 VBUS_ADC1 Register

7	6	5	4	3	2	1	0
VBUS_POL	VBUS_ADC[14:8]
R-x	R-x

Table 9-30 VBUS_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset By WATCHDOG	Bit Value	Description
7	VBUS_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	VBUS_ADC[14]	R	x	Y	N/A	16384 mV	Voltage of VBUS
5	VBUS_ADC[13]	R	x	Y	N/A	8192 mV
4	VBUS_ADC[12]	R	x	Y	N/A	4096 mV
3	VBUS_ADC[11]	R	x	Y	N/A	2048 mV
2	VBUS_ADC[10]	R	x	Y	N/A	1024 mV
1	VBUS_ADC[9]	R	x	Y	N/A	512 mV
0	VBUS_ADC[8]	R	x	Y	N/A	256 mV

9.6.1.26 VBUS_ADC0 Register (Address = 19h) [reset = xh]

VBUS_ADC0 is shown in Figure 9-38 and described in Table 9-31.

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All bits are RESET BY REG_RST.

Figure 9-38 VBUS_ADC0 Register

7	6	5	4	3	2	1	0
VBUS_ADC[7:0]
R-x

Table 9-31 VBUS_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset By REG_RST	Reset By WATCHDOG	Bit Value
7	VBUS_ADC[7]	R	x	Y	N/A	128 mV
6	VBUS_ADC[6]	R	x	Y	N/A	64 mV
5	VBUS_ADC[5]	R	x	Y	N/A	32 mV
4	VBUS_ADC[4]	R	x	Y	N/A	16 mV
3	VBUS_ADC[3]	R	x	Y	N/A	8 mV
2	VBUS_ADC[2]	R	x	Y	N/A	4 mV
1	VBUS_ADC[1]	R	x	Y	N/A	2 mV
0	VBUS_ADC[0]	R	x	Y	N/A	1 mV

9.6.1.27 VAC_ADC1 Register (Address = 1Ah) [reset = xh]

VAC_ADC1 is shown in Figure 9-39 and described in Table 9-32.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-39 VAC_ADC1 Register

7	6	5	4	3	2	1	0
VAC_POL	VAC_ADC[14:8]
R-x	R-x

Table 9-32 VAC_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	VAC_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	VAC_ADC[14]	R	x	Y	N/A	16384 mV	Voltage of VAC
5	VAC_ADC[13]	R	x	Y	N/A	8192 mV
4	VAC_ADC[12]	R	x	Y	N/A	4096 mV
3	VAC_ADC[11]	R	x	Y	N/A	2048 mV
2	VAC_ADC[10]	R	x	Y	N/A	1024 mV
1	VAC_ADC[9]	R	x	Y	N/A	512 mV
0	VAC_ADC[8]	R	x	Y	N/A	256 mV

9.6.1.28 VAC_ADC0 Register (Address = 1Bh) [reset = xh]

VAC_ADC0 is shown in Figure 9-40 and described in Table 9-33.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-40 VAC_ADC0 Register

7	6	5	4	3	2	1	0
VAC_ADC[7:0]
R-x

Table 9-33 VAC_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	VAC_ADC[7]	R	x	Y	N/A	128 mV
6	VAC_ADC[6]	R	x	Y	N/A	64 mV
5	VAC_ADC[5]	R	x	Y	N/A	32 mV
4	VAC_ADC[4]	R	x	Y	N/A	16 mV
3	VAC_ADC[3]	R	x	Y	N/A	8 mV
2	VAC_ADC[2]	R	x	Y	N/A	4 mV
1	VAC_ADC[1]	R	x	Y	N/A	2 mV
0	VAC_ADC[0]	R	x	Y	N/A	1 mV

9.6.1.29 VOUT_ADC1 Register (Address = 1Ch) [reset = xh]

VOUT_ADC1 is shown in Figure 9-41 and described in Table 9-34.

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All bits are RESET BY REG_RST.

Figure 9-41 VOUT_ADC1 Register

7	6	5	4	3	2	1	0
VOUT_POL	VOUT_ADC[14:8]
R-x	R-x

Table 9-34 VOUT_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	VOUT_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	VOUT_ADC[14]	R	x	Y	N/A	16384 mV	Voltage of VOUT
5	VOUT_ADC[13]	R	x	Y	N/A	8192 mV
4	VOUT_ADC[12]	R	x	Y	N/A	4096 mV
3	VOUT_ADC[11]	R	x	Y	N/A	2048 mV
2	VOUT_ADC[10]	R	x	Y	N/A	1024 mV
1	VOUT_ADC[9]	R	x	Y	N/A	512 mV
0	VOUT_ADC[8]	R	x	Y	N/A	256 mV

9.6.1.30 VOUT_ADC0 Register (Address = 1Dh) [reset = xh]

VOUT_ADC0 is shown in Figure 9-42 and described in Table 9-35.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-42 VOUT_ADC0 Register

7	6	5	4	3	2	1	0
VOUT_ADC[7:0]
R-x

Table 9-35 VOUT_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	VOUT_ADC[7]	R	x	Y	N/A	128 mV
6	VOUT_ADC[6]	R	x	Y	N/A	64 mV
5	VOUT_ADC[5]	R	x	Y	N/A	32 mV
4	VOUT_ADC[4]	R	x	Y	N/A	16 mV
3	VOUT_ADC[3]	R	x	Y	N/A	8 mV
2	VOUT_ADC[2]	R	x	Y	N/A	4 mV
1	VOUT_ADC[1]	R	x	Y	N/A	2 mV
0	VOUT_ADC[0]	R	x	Y	N/A	1 mV

9.6.1.31 VBAT_ADC1 Register (Address = 1Eh) [reset = xh]

VBAT_ADC1 is shown in Figure 9-43 and described in Table 9-36.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-43 VBAT_ADC1 Register

7	6	5	4	3	2	1	0
VBAT_POL	VBAT_ADC[14:8]
R-x	R-x

Table 9-36 VBAT_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	VBAT_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	VBAT_ADC[14]	R	x	Y	N/A	16384 mV	Voltage of VBAT
5	VBAT_ADC[13]	R	x	Y	N/A	8192 mV
4	VBAT_ADC[12]	R	x	Y	N/A	4096 mV
3	VBAT_ADC[11]	R	x	Y	N/A	2048 mV
2	VBAT_ADC[10]	R	x	Y	N/A	1024 mV
1	VBAT_ADC[9]	R	x	Y	N/A	512 mV
0	VBAT_ADC[8]	R	x	Y	N/A	256 mV

9.6.1.32 VBAT_ADC0 Register (Address = 1Fh) [reset = xh]

VBAT_ADC0 is shown in Figure 9-44 and described in Table 9-37.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-44 VBAT_ADC0 Register

7	6	5	4	3	2	1	0
VBAT_ADC[7:0]
R-x

Table 9-37 VBAT_ADC0 Register Field Descriptions

Bit	Field	Type	Reset	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	VBAT_ADC[7]	R	x	Y	N/A	128 mV
6	VBAT_ADC[6]	R	x	Y	N/A	64 mV
5	VBAT_ADC[5]	R	x	Y	N/A	32 mV
4	VBAT_ADC[4]	R	x	Y	N/A	16 mV
3	VBAT_ADC[3]	R	x	Y	N/A	8 mV
2	VBAT_ADC[2]	R	x	Y	N/A	4 mV
1	VBAT_ADC[1]	R	x	Y	N/A	2 mV
0	VBAT_ADC[0]	R	x	Y	N/A	1 mV

9.6.1.33 IBAT_ADC1 Register (Address = 20h) [reset = xh]

IBAT_ADC1 is shown in Figure 9-45 and described in Table 9-38.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-45 IBAT_ADC1 Register

7	6	5	4	3	2	1	0
IBAT_POL	IBAT_ADC[14:8]
R-x	R-x

Table 9-38 IBAT_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	IBAT_POL	R	x	Y	N/A	N/A	Positive is charging and negative is discharging. Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	IBAT_ADC[14]	R	x	Y	N/A	16384 mA	Current of IBAT
5	IBAT_ADC[13]	R	x	Y	N/A	8192 mA
4	IBAT_ADC[12]	R	x	Y	N/A	4096 mA
3	IBAT_ADC[11]	R	x	Y	N/A	2048 mA
2	IBAT_ADC[10]	R	x	Y	N/A	1024 mA
1	IBAT_ADC[9]	R	x	Y	N/A	512 mA
0	IBAT_ADC[8]	R	x	Y	N/A	256 mA

9.6.1.34 IBAT_ADC0 Register (Address = 21h) [reset = xh]

IBAT_ADC0 is shown in Figure 9-46 and described in Table 9-39.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-46 IBAT_ADC0 Register

7	6	5	4	3	2	1	0
IBAT_ADC[7:0]
R-x

Table 9-39 IBAT_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	IBAT_ADC[7]	R	x	Y	N/A	128 mA
6	IBAT_ADC[6]	R	x	Y	N/A	64 mA
5	IBAT_ADC[5]	R	x	Y	N/A	32 mA
4	IBAT_ADC[4]	R	x	Y	N/A	16 mA
3	IBAT_ADC[3]	R	x	Y	N/A	8 mA
2	IBAT_ADC[2]	R	x	Y	N/A	4 mA
1	IBAT_ADC[1]	R	x	Y	N/A	2 mA
0	IBAT_ADC[0]	R	x	Y	N/A	1 mA

9.6.1.35 TSBUS_ADC1 Register (Address = 22h) [reset = xh]

TSBUS_ADC1 is shown in Figure 9-47 and described in Table 9-40.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-47 TSBUS_ADC1 Register

7	6	5	4	3	2	1	0
TSBUS_POL	TSBUS_ADC[14:8]
R-x	R-x

Table 9-40 TSBUS_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TSBUS_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	TSBUS_ADC[14]	R	x	Y	N/A		TSBUS Pin Voltage as a Percentage of VOUT TSBUS Percentage = TSBUS_ADC[8:0] x 0.09766%
5	TSBUS_ADC[13]	R	x	Y	N/A
4	TSBUS_ADC[12]	R	x	Y	N/A
3	TSBUS_ADC[11]	R	x	Y	N/A
2	TSBUS_ADC[10]	R	x	Y	N/A
1	TSBUS_ADC[9]	R	x	Y	N/A	50%
0	TSBUS_ADC[8]	R	x	Y	N/A	25%

9.6.1.36 TSBUS_ADC0 Register (Address = 23h) [reset = xh]

TSBUS_ADC0 is shown in Figure 9-48 and described in Table 9-41.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-48 TSBUS_ADC0 Register

7	6	5	4	3	2	1	0
TSBUS_ADC[7:0]
R-x

Table 9-41 TSBUS_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	TSBUS_ADC[7]	R	x	Y	N/A	12.5%
6	TSBUS_ADC[6]	R	x	Y	N/A	6.25%
5	TSBUS_ADC[5]	R	x	Y	N/A	3.125%
4	TSBUS_ADC[4]	R	x	Y	N/A	1.5625%
3	TSBUS_ADC[3]	R	x	Y	N/A	0.78125%
2	TSBUS_ADC[2]	R	x	Y	N/A	0.39063%
1	TSBUS_ADC[1]	R	x	Y	N/A	0.19531%
0	TSBUS_ADC[0]	R	x	Y	N/A	0.09766%

9.6.1.37 TSBAT_ADC1 Register (Address = 24h) [reset = xh]

TSBAT_ADC1 is shown in Figure 9-49 and described in Table 9-42.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-49 TSBAT_ADC1 Register

7	6	5	4	3	2	1	0
TSBAT_POL	TSBAT_ADC[14:8]
R-x	R-x

Table 9-42 TSBAT_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TSBAT_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0b = Result is positive 1b = Result is negative
6	TSBAT_ADC[14]	R	x	Y	N/A
5	TSBAT_ADC[13]	R	x	Y	N/A
4	TSBAT_ADC[12]	R	x	Y	N/A
3	TSBAT_ADC[11]	R	x	Y	N/A
2	TSBAT_ADC[10]	R	x	Y	N/A
1	TSBAT_ADC[9]	R	x	Y	N/A	50%
0	TSBAT_ADC[8]	R	x	Y	N/A	25%

9.6.1.38 TSBAT_ADC0 Register (Address = 25h) [reset = xh]

TSBAT_ADC0 is shown in Figure 9-50 and described in Table 9-43.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-50 TSBAT_ADC0 Register

7	6	5	4	3	2	1	0
TSBAT_ADC[7:0]
R-x

Table 9-43 TSBAT_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TSBAT_ADC[7]	R	x	Y	N/A	12.5%	TSBAT Pin Voltage as a Percentage of VOUT TSBAT Percentage = TSBAT_ADC[8:0] x 0.09766%
6	TSBAT_ADC[6]	R	x	Y	N/A	6.25%
5	TSBAT_ADC[5]	R	x	Y	N/A	3.125%
4	TSBAT_ADC[4]	R	x	Y	N/A	1.5625%
3	TSBAT_ADC[3]	R	x	Y	N/A	0.78125%
2	TSBAT_ADC[2]	R	x	Y	N/A	0.39063%
1	TSBAT_ADC[1]	R	x	Y	N/A	0.19531%
0	TSBAT_ADC[0]	R	x	Y	N/A	0.09766%

9.6.1.39 TDIE_ADC1 Register (Address = 26h) [reset = xh]

TDIE_ADC1 is shown in Figure 9-51 and described in Table 9-44.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-51 TDIE_ADC1 Register

7	6	5	4	3	2	1	0
TDIE_POL	TDIE_ADC[14:8]
R-x	R-x

Table 9-44 TDIE_ADC1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TDIE_POL	R	x	Y	N/A	N/A	Reported in Two's Complement. 0 = Result is positive 1 = Result is negative
6	TDIE_ADC[14]	R	x	Y	N/A		DIE Temperature = 5°C + TDIE_ADC[8:0] * 0.5°C
5	TDIE_ADC[13]	R	x	Y	N/A
4	TDIE_ADC[12]	R	x	Y	N/A
3	TDIE_ADC[11]	R	x	Y	N/A
2	TDIE_ADC[10]	R	x	Y	N/A
1	TDIE_ADC[9]	R	x	Y	N/A
0	TDIE_ADC[8]	R	x	Y	N/A	128°C

9.6.1.40 TDIE_ADC0 Register (Address = 27h) [reset = xh]

TDIE_ADC0 is shown in Figure 9-52 and described in Table 9-45.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-52 TDIE_ADC0 Register

7	6	5	4	3	2	1	0
TDIE_ADC[7:0]
R-x

Table 9-45 TDIE_ADC0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value
7	TDIE_ADC[7]	R	x	Y	N/A	64°C
6	TDIE_ADC[6]	R	x	Y	N/A	32°C
5	TDIE_ADC[5]	R	x	Y	N/A	16°C
4	TDIE_ADC[4]	R	x	Y	N/A	8°C
3	TDIE_ADC[3]	R	x	Y	N/A	4°C
2	TDIE_ADC[2]	R	x	Y	N/A	2°C
1	TDIE_ADC[1]	R	x	Y	N/A	1°C
0	TDIE_ADC[0]	R	x	Y	N/A	0.5°C

9.6.1.41 TSBUS_FLT1 Register (Address = 28h) [reset = 15h]

TSBUS_FLT1 is shown in Figure 9-53 and described in Table 9-46.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-53 TSBUS_FLT1 Register

7	6	5	4	3	2	1	0
TSBUS_FLT[7:0]
R/W-75h

Table 9-46 TSBUS_FLT1 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TSBUS_FLT[7]	R/W	0h	Y	N	25.00%	TSBUS Percentage Fault Threshold A TSBUS_TSBAT_ALM interrupt will be sent when TSBUS is within 5% of the value set in this register TSBUS_FLT = TSBUS_FLT[7:0] x 0.19531% Default: 4.1% (b00010101)
6	TSBUS_FLT[6]	R/W	0h	Y	N	12.5%
5	TSBUS_FLT[5]	R/W	0h	Y	N	6.25%
4	TSBUS_FLT[4]	R/W	1h	Y	N	3.125%
3	TSBUS_FLT[3]	R/W	0h	Y	N	1.5625%
2	TSBUS_FLT[2]	R/W	1h	Y	N	0.78125%
1	TSBUS_FLT[1]	R/W	0h	Y	N	0.39063%
0	TSBUS_FLT[0]	R/W	1h	Y	N	0.19531%

9.6.1.42 TSBAT_FLT0 Register (Address = 29h) [reset = 15h]

TSBAT_FLT0 is shown in Figure 9-54 and described in Table 9-47.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-54 TSBAT_FLT0 Register

7	6	5	4	3	2	1	0
TSBAT_FLT[7:0]
R/W-75h

Table 9-47 TSBAT_FLT0 Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TSBAT_FLT[7]	R/W	0	Y	N	25.00%	TSBAT Percentage Fault Threshold A TSBUS_TSBAT_ALM interrupt will be sent when TSBAT is within 5% of the value set in this register. TSBAT_FLT = TSBAT_FLT[7:0] x 0.19531% Default: 4.1% (b00010101)
6	TSBAT_FLT[6]	R/W	0	Y	N	12.5%
5	TSBAT_FLT[5]	R/W	0	Y	N	6.25%
4	TSBAT_FLT[4]	R/W	1	Y	N	3.125%
3	TSBAT_FLT[3]	R/W	0	Y	N	1.5625%
2	TSBAT_FLT[2]	R/W	1	Y	N	0.78125%
1	TSBAT_FLT[1]	R/W	0	Y	N	0.39063%
0	TSBAT_FLT[0]	R/W	1	Y	N	0.19531%

9.6.1.43 TDIE_ALM Register (Address = 2Ah) [reset = C8h]

TDIE_ALM is shown in Figure 9-55 and described in Table 9-48.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-55 TDIE_ALM Register

7	6	5	4	3	2	1	0
TDIE_ALM[7:0]
R/W-A8h

Table 9-48 TDIE_ALM Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	TDIE_ALM[7]	R/W	1h	Y	N	64°C	TDIE Voltage Fault Threshold If the value written to the register is greater than the max or less than the min defined value, the register will be set to the maximum or minimum as necessary. TDIE_ALM = 30 + TDIE_FLT[7:0] x 0.5°C Default: 125C (b11001000)
6	TDIE_ALM[6]	R/W	1h	Y	N	32°C
5	TDIE_ALM[5]	R/W	0h	Y	N	16°C
4	TDIE_ALM[4]	R/W	0h	Y	N	8°C
3	TDIE_ALM[3]	R/W	1h	Y	N	4°C
2	TDIE_ALM[2]	R/W	0h	Y	N	2°C
1	TDIE_ALM[1]	R/W	0h	Y	N	1°C
0	TDIE_ALM[0]	R/W	0h	Y	N	0.5°C

9.6.1.44 CHG_CTRL Register (Address = 2Bh) [reset = 0h]

Figure 9-56 CHG_CTRL Register

7	6	5	4	3	2	1	0
SS_TIMEOUT_SET2	SS_TIMEOUT_SET1	SS_TIMEOUT_SET0	RESERVED	VOUT_OVP_DIS	IBUS_UCP_RISE_THRE	SET_IBAT_SNS_RES	VAC_PD_EN
R/W - 0h			R-x	R/W - 0h

Table 9-49 CHG_CTRL Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	SS_TIMEOUT_SET2	R/W	0h	N	N	N/A	Adjustable timeout for IBUS to rise to IBUS_UCP_RISE_THRESH 000: Timeout Disabled 001: 12.5 ms 010: 25 ms 011: 50 ms 100: 100 ms 101: 400 ms 110: 1.5 s 111: 100 s
6	SS_TIMEOUT_SET1	R/W	0h	N	N	N/A
5	SS_TIMEOUT_SET0	R/W	0h	N	N	N/A
4	RESERVED	R	x	N	N	N/A	RESERVED
3	VOUT_OVP_DIS	R/W	0h	N	N	N/A	This register disables the VOUT_OVP function.
2	IBUS_UCP_RISE_THRESH	R/W	0h	Y	N	N/A	This is the threshold above which the BUS current must rise to within the SS_TIMEOUT. The value can only be changed prior to enabling switching.0: 300 mA rising, 150 mA falling (typ)1: 500 mA rising, 250 mA falling (typ)
1	SET_IBAT_SNS_RES	R/W	0h	N	N	N/A	This bit selects the external BAT_SNS resistor value. 0: 2 mΩ 1: 5 mΩ
0	VAC_PD_EN	R/W	0h	Y	N	N/A	When this bit is enabled, it pulls down the VAC for t_{VAC_PD} to discharge any bulk input cap on VAC.

9.6.1.45 VOUT_OVP_STAT Register (Address = 2Ch) [reset = 0h]

Figure 9-57 VOUT_OVP_STAT Register

7	6	5	4	3	2	1	0
RESERVED							VOUT_OVP_STAT
R-x

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-50 VOUT_OVP_STAT Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7-1	RESERVED	R	x	N	N	N/A	RESERVED
0	VOUT_OVP_STAT	R	x	N	N	N/A	Ths bit is set when VOUT_OVP is active. It is cleared when VOUT_OVP is no longer active.

9.6.1.46 VOUT_FLAG_MASK Register (Address = 2Dh) [reset = 0h]

Figure 9-58 VOUT_FLAG_MASK Register

7	6	5	4	3	2	1	0
RESERVED			VOUT_OVP_FLAG	RESERVED			VOUT_OVP_MASK
R-X							R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-51 VOUT_FLAG_MASK Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7-5	RESERVED	R	x	N	N	N/A	RESERVED
4	VOUT_OVP_FLAG	R	x	N	N	N/A	This bit is set when VOUT_OVP has been active. It is cleared by a read and VOUT_OVP is no longer active.
3-1	RESERVED	R	x	N	N	N/A	RESERVED
0	VOUT_OVP_MASK	R/W	0h	Y	N	N/A	This register masks the interrupt when the part enters exceeds the VOUT_OVP threshold000REG.

9.6.1.47 DEGLITCH Register (Address = 2Eh) [reset = 0h]

PULSE_MODE is shown in Figure 9-59 and described in Table 9-52.

Return to Summary Table.

All bits are RESET BY REG_RST.

Figure 9-59 Deglitch Register

7	6	5	4	3	2	1	0
RESERVED			VBUS_ERROR_LO_DG_SET	IBUS_LOW_DG_SET	RESERVED
R/W-0h			R/W-0h	R/W-0h	R/W-0h

Table 9-52 Deglitch Register Field Descriptions

Bit	Field	Type	Reset or Default	Reset by REG_RST	Reset by WATCHDOG	Bit Value	Description
7	RESERVED		0h
6			0h
5			0h
4	VBUS_ERROR_LO_DG_SET	R/W	0h	Y	N	N/A	This bit sets the deglitch time for VBUS_ERROR_LO0: 10 µs, 1: 10 ms
3	IBUS_LOW_DG_SET	R/W	0h	Y	N	N/A	Ths bit sets the deglitch time for IBUS_LOW_DG_SET0: 10 µs, 1: 5 ms
2	RESERVED		0h
1			0h
0			0h

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発注情報

9.6.1 Customer Registers

9.6.1.1 BAT_OVP Register (Address = 0h) [reset = 22h]

9.6.1.2 BAT_OVP_ALM Register (Address = 1h) [reset = 1Ch]

9.6.1.3 BAT_OCP Register (Address = 2h) [reset = 3Dh]

9.6.1.4 BAT_OCP_ALM Register (Address = 3h) [reset = 3Ch]

9.6.1.5 BAT_UCP_ALM Register (Address = 4h) [reset = 28h]

9.6.1.6 AC_PROTECTION Register (Address = 5h) [reset = 3h]

9.6.1.7 BUS_OVP Register (Address = 6h) [reset = 3Ah]

9.6.1.8 BUS_OVP_ALM Register (Address = 7h) [reset = 38h]

9.6.1.9 BUS_OCP_UCP Register (Address = 8h) [reset = Dh]

9.6.1.10 BUS_OCP_ALM Register (Address = 9h) [reset = 50h]

9.6.1.11 CONVERTER_STATE Register (Address = Ah) [reset = 0h]

9.6.1.12 CONTROL Register (Address = Bh) [reset = 40h]

9.6.1.13 CHRG_CTRL Register (Address = Ch) [reset = 0h]

9.6.1.14 INT_STAT Register (Address = Dh) [reset = xh]

9.6.1.15 INT_FLAG Register (Address = Eh) [reset = xh]

9.6.1.16 INT_MASK Register (Address = Fh) [reset = 0h]

9.6.1.17 FLT_STAT Register (Address = 10h) [reset = xh]

9.6.1.18 FLT_FLAG Register (Address = 11h) [reset = xh]

9.6.1.19 FLT_MASK Register (Address = 12h) [reset = 0h]

9.6.1.20 PART_INFO Register (Address = 13h) [reset = xh]

9.6.1.21 ADC_CTRL Register (Address = 14h) [reset = xh]

9.6.1.22 ADC_FN_DISABLE Register (Address = 15h) [reset = 0h]

9.6.1.23 IBUS_ADC1 Register (Address = 16h) [reset = xh]

9.6.1.24 IBUS_ADC0 Register (Address = 17h) [reset = xh]

9.6.1.25 VBUS_ADC1 Register (Address = 18h) [reset = xh]

9.6.1.26 VBUS_ADC0 Register (Address = 19h) [reset = xh]

9.6.1.27 VAC_ADC1 Register (Address = 1Ah) [reset = xh]

9.6.1.28 VAC_ADC0 Register (Address = 1Bh) [reset = xh]

9.6.1.29 VOUT_ADC1 Register (Address = 1Ch) [reset = xh]

9.6.1.30 VOUT_ADC0 Register (Address = 1Dh) [reset = xh]

9.6.1.31 VBAT_ADC1 Register (Address = 1Eh) [reset = xh]

9.6.1.32 VBAT_ADC0 Register (Address = 1Fh) [reset = xh]

9.6.1.33 IBAT_ADC1 Register (Address = 20h) [reset = xh]

9.6.1.34 IBAT_ADC0 Register (Address = 21h) [reset = xh]

9.6.1.35 TSBUS_ADC1 Register (Address = 22h) [reset = xh]

9.6.1.36 TSBUS_ADC0 Register (Address = 23h) [reset = xh]

9.6.1.37 TSBAT_ADC1 Register (Address = 24h) [reset = xh]

9.6.1.38 TSBAT_ADC0 Register (Address = 25h) [reset = xh]

9.6.1.39 TDIE_ADC1 Register (Address = 26h) [reset = xh]

9.6.1.40 TDIE_ADC0 Register (Address = 27h) [reset = xh]

9.6.1.41 TSBUS_FLT1 Register (Address = 28h) [reset = 15h]

9.6.1.42 TSBAT_FLT0 Register (Address = 29h) [reset = 15h]

9.6.1.43 TDIE_ALM Register (Address = 2Ah) [reset = C8h]

9.6.1.44 CHG_CTRL Register (Address = 2Bh) [reset = 0h]

9.6.1.45 VOUT_OVP_STAT Register (Address = 2Ch) [reset = 0h]

9.6.1.46 VOUT_FLAG_MASK Register (Address = 2Dh) [reset = 0h]

9.6.1.47 DEGLITCH Register (Address = 2Eh) [reset = 0h]