JAJSVF7 October   2024 BQ51013C

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Details of a Qi Wireless Power System and BQ51013C Power Transfer Flow Diagrams
      2. 8.3.2  Dynamic Rectifier Control
      3. 8.3.3  Dynamic Efficiency Scaling
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Input Overvoltage
      6. 8.3.6  Adapter Enable Functionality and EN1/EN2 Control
      7. 8.3.7  End Power Transfer Packet (WPC Header 0x02)
      8. 8.3.8  Status Outputs
      9. 8.3.9  WPC Communication Scheme
      10. 8.3.10 Communication Modulator
      11. 8.3.11 Adaptive Communication Limit
      12. 8.3.12 Synchronous Rectification
      13. 8.3.13 Temperature Sense Resistor Network (TS)
      14. 8.3.14 3-State Driver Recommendations for the TS/CTRL Pin
      15. 8.3.15 Thermal Protection
      16. 8.3.16 WPC v2.0 Compliance – Foreign Object Detection
      17. 8.3.17 Receiver Coil Load-Line Analysis
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 BQ51013C Wireless Power Receiver Used as a Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Using The BQ51013C as a Wireless Power Supply: (See Figure 1-1 )
          2. 9.2.1.2.2 Series and Parallel Resonant Capacitor Selection
          3. 9.2.1.2.3 Recommended RX Coils
          4. 9.2.1.2.4 COMM, CLAMP, and BOOT Capacitors
          5. 9.2.1.2.5 Control Pins and CHG
          6. 9.2.1.2.6 Current Limit and FOD
          7. 9.2.1.2.7 RECT and OUT Capacitance
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual Power Path: Wireless Power and DC Input
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Wireless and Direct Charging of a Li-Ion Battery at 800 mA
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
      2. 12.1.2 Development Support
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

8.3.9 WPC Communication Scheme

The WPC communication uses a modulation technique termed “back-scatter modulation” where the receiver coil is dynamically loaded in order to provide amplitude modulation of the transmitter's coil voltage and current. This scheme is possible due to the fundamental behavior between two loosely coupled inductors (here between the TX and RX coils). This type of modulation can be accomplished by switching in and out a resistor at the output of the rectifier, or by switching in and out a capacitor across the AC1/AC2 net. Figure 8-4 shows how to implement resistive modulation.

BQ51013C Resistive ModulationFigure 8-4 Resistive Modulation

Figure 8-5 shows how to implement capacitive modulation.

BQ51013C Capacitive ModulationFigure 8-5 Capacitive Modulation

The amplitude change in the TX coil voltage or current can be detected by the transmitter's decoder. The resulting signal observed by the TX is shown in Figure 8-6.

BQ51013C TX Coil Voltage/Current Figure 8-6 TX Coil Voltage/Current

The WPC protocol uses a differential bi-phase encoding scheme to modulate the data bits onto the TX coil voltage/current. Each data bit is aligned at a full period of 0.5 ms (tCLK) or 2 kHz. An encoded ONE results in two transitions during the bit period and an encoded ZERO results in a single transition. See Figure 8-7 for an example of the differential bi-phase encoding.

BQ51013C Differential Bi-Phase Encoding Scheme (WPC Volume 1: Low Power, Part 1 Interface Definition)Figure 8-7 Differential Bi-Phase Encoding Scheme (WPC Volume 1: Low Power, Part 1 Interface Definition)

The bits are sent LSB first and use an 11-bit asynchronous serial format for each portion of the packet. This includes one start bit, n-data bytes, a parity bit, and a single stop bit. The start bit is always ZERO and the parity bit is odd. The stop bit is always ONE. Figure 8-8 shows the details of the asynchronous serial format.

BQ51013C Asynchronous Serial Formatting (WPC Volume 1: Low Power, Part 1 Interface Definition)Figure 8-8 Asynchronous Serial Formatting (WPC Volume 1: Low Power, Part 1 Interface Definition)

Each packet format is organized as shown in Figure 8-9.

BQ51013C Packet Format (WPC Volume 1: Low Power, Part 1 Interface Definition)Figure 8-9 Packet Format (WPC Volume 1: Low Power, Part 1 Interface Definition)

Figure 7-20 shows an example waveform of the receiver sending a rectified power packet (header 0x04).