JAJSU42A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RSN|32
サーマルパッド・メカニカル・データ
発注情報

8.6 Unused Pins

Some device pins may not be needed in a particular application. Table 8-3 shows recommendations in which each should be terminated in this case.

Table 8-3 Terminating Unused Pins
Pin Name Recommendation
2–9 VC0–VC5 Cell inputs 1, 2, and 5 should always be connected to actual cells, with cells connected between VC1 and VC0, VC2 and VC1, and VC4A and VC5. VC0 should be connected through a resistor and capacitor on the pcb to pin 10 (VSS). Pins related to unused cells (which may be cell 3–cell 4, pins 3–6) can be connected to the cell stack to measure interconnect resistance or provide a Kelvin-connection to actual cells, in which case they should include a series resistor and parallel capacitor, in similar fashion to pins connected to actual cells (see Usage of VC Pins for Cells Versus Interconnect). Another option is to short unused VC pins directly to an adjacent VC pin. All VC pins should be connected to either an adjacent VC pin, an actual cell (through R and C) or stack interconnect resistance (through R and C).
11–12 SRP, SRN If not used, these pins should be connected to pin 10 (VSS).
13, 16, 19, 20 TS1, ALERT, CFETOFF, DFETOFF If not used, these pins can be left floating or connected to pin 10 (VSS). Any of these pins except for TS1 may be configured with the internal weak pulldown resistance enabled during operation, although this is not necessary.
14 TS2 If the device is intended to enter SHUTDOWN mode, the TS2 pin should be left floating. If SHUTDOWN mode will not be used in the application, and the TS2 pin will not be used for a thermistor or ADCIN measurement, the TS2 pin can be left floating or connected to pin 10 (VSS).
21 RST_SHUT If not used, this pin should be connected to pin 10 (VSS).
22 REG1 If not used, this pin can be left floating or connected to pin 10 (VSS).
23 REGIN If not used, this pin should be connected to pin 10 (VSS).
24 BREG If this pin is not used and pin 23 (REGIN) is also not used, both pins should be connected to pin 10 (VSS). If this pin is not used but pin 23 is used (such as driven from an external source), then this pin should be connected to pin 23 (REGIN).
25 FUSE If not used, this pin can be left floating or connected to pin 10 (VSS).
26 PDSG If not used, this pin should be left floating.
27 PCHG If not used, this pin should be left floating.
28 LD If the DSG driver will not be used, this pin can be connected through a series resistor to the PACK+ connector, or can be connected to pin 10 (VSS).
30 DSG If not used, this pin should be left floating.
31 CHG If not used, this pin should be left floating.
32 CP1 If not used, this pin should be connected to pin 1 (BAT).
Note: If the charge pump is enabled with CP1 connected to BAT, the device will consume an additional ≈200 µA.