JAJSU42A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RSN|32
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発注情報

6.18 Analog-to-Digital Converter

Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(ADC_IN_CELLS) Input voltage range (differential cell input mode)(4) Internal reference (Vref = VREF1) –0.2 5.5 V
V(ADC_IN) Input voltage range (ADCIN measurement mode)(5) Internal reference (Vref = VREF1), applicable to ADCIN measurements using the TS1, TS2, ALERT, CFETOFF, and DFETOFF pins –0.2 VREG18 V
V(ADC_IN_TS) Input voltage range (external thermistor measurement mode)(6) Regulator reference (Vref = VREG18), applicable to external thermistor measurements using the TS1, TS2, ALERT, CFETOFF, and DFETOFF pins –0.2 VREG18 V
V(ADC_IN_DIV) Input voltage range (divider measurement mode)(7) Internal reference (Vref = VREF1), applicable to divider measurements using the VC5, PACK, and LD pins relative to VSS. –0.2 27.5 V
B(ADC_INL) Integral nonlinearity (when using VREF1 and differential cell voltage measurement mode at VC5 - VC4A)(3) 16-bit, best fit over -0.1 V to 5.5 V –6.6 6.6 LSB(4)
16-bit, best fit over -0.2 V to 0.2 V –4 4 LSB(4)
B(ADC_DNL) Differential nonlinearity 16-bit, no missing codes, using differential cell voltage measurement at VC5 - VC4A ±0.12 LSB(4)
B(ADC_OFF_CELL) Differential cell offset error(3) 16-bit, uncalibrated, using VC5 - VC4A –2.75 3.5 LSB(4)
B(ADC_OFF) ADCIN offset error 16-bit, uncalibrated, using ADCIN mode on TS1 pin 0.53 LSB(5)
B(ADC_OFF_DIV) Divider offset error 16-bit, uncalibrated, using divider mode on PACK pin 0.17 LSB(7)
B(ADC_OFF_DRIFT_CELL) Differential cell offset error drift Offset error measured 16-bit, post calibration, using VC5 - VC4A.  Drift measured as change in offset over operating temperature range as compared to offset at 30°C. 0.004 LSB/°C(4)
B(ADC_GAIN) Gain Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC5 - VC4A, uncalibrated. 5385 5406 5427 LSB/V(4)
B(ADC_GAIN_DRIFT) Gain drift(3) Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC5 - VC4A, uncalibrated.  Drift value measured as change in gain over operating temperature range, compared to gain at 30°C. –0.25 0.025 0.25 LSB/V/°C(4)
R(ADC_IN_CELL) Effective input resistance(2) Differential cell input mode on VC5 - VC4A(8) 2.1 MΩ
R(ADC_IN_LD) Effective input resistance Divider measurement on LD pin (only active while the LD pin is being measured) 2 MΩ
R(ADC_IN_DIV) Effective input resistance Divider measurement on VC5 and PACK pins (only active while the pin is being measured) 600 kΩ
B(ADC_RES) Code stability(1)(3) Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 13.5 15 bits
B(ADC_RES_FAST) Code stability in fast mode(1) Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 14 bits
t(ADC_CONV) Conversion-time Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 2.93 ms
t(ADC_CONV_FAST) Conversion-time in fast mode Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 1.46 ms
(1) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.
(2) Specified by design
(3) Specified by characterization
(4) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x VREF1 / 2N-1 ≈ 5 x 1.215 V / 215 = 185 µV
(5) The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x VREF1 / 2N-1 ≈ 5 / 3 x 1.215 V / 215 = 62 µV
(6) The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x VREG18 / 2N-1 ≈ 5 / 3 x 1.8 V / 223 = 358 nV
(7) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x VREF1 / 2N-1 ≈ 425 / 3 x 1.215 / 223 = 5.25 mV
(8) Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, three or more thermistors in use, and a 5 V differential voltage applied.