JAJSCB2K April   2020  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.1 Design Example

To design the protection for a 36-V Li-ion battery pack using 4.2-V LiCoO2 cells with the following protection requirements:

Voltage Protection

  • OV at 4.3 V, recover at 4.1 V
  • UV at 2.6 V, recover at 3 V and when load is removed.

Current Protection

  • OCD1 at 40 A with 300-ms–400-ms delay
  • OCD2 at 80 A with the shortest delay option
  • SCD at 100 A with < 500-µs delay
  • Requires load removal for recovery

Temperature Protection

  • Charge – OTC at 50°C, UTC at –5°C
  • Discharge – OTD at 70°C, UTD at –10°C

To start the design:

  1. Start the schematic.
    • A 36-V pack using LiCoO2 cells requires 10-S configuration; thus, two BQ77905 devices in a stackable configuration is needed.
    • Follow the 10-S reference schematic in this document. Follow the recommended design parameters listed in the Section 9.2.1 section of this document.
    • The power FET used in this type of application usually has an absolute of 20 V Vgs. For a 36-V pack design, TI recommends to use the additional components to protect the CHG FET Vgs. See the Section 9.1.1.4 section for details.
    • Because load removal for UV recovery is required, a 3-MΩ RGS_CHG should be used for the schematic.
  2. Decide the value of the sense resistor, RSNS.
    • When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available current protection threshold range.
    • In this example, select RSNS = 1 mΩ (any value ≤ 2 mΩ will work in this example).
  3. Determine all of the BQ77905 protection configurations (see Table 9-2).
  4. Review the available released or preview devices in the Section 5 section to determine if a suitable option is available. If not, contact TI representative for further assistance.

Table 9-2 Design Example Configuration
ProtectionThresholdHysteresisDelayRecovery Method
OV4.3 V200 mV1 s (default setting)Hysteresis
UV2.6 V400 mV1 s (default setting)Hysteresis + load removal
OW100 nA
(default setting)		——(VCx – VCx–1) > 600 mV (typical)
OCD140 mV—350 msLoad removal only
OCD280 mV—5 msLoad removal only
SCD100 mV—Fixed at 360 µsLoad removal only
OTC50°C10°C4.5 sHysteresis
OTD70°C10°C4.5 sHysteresis
UTC–5°C10°C4.5 sHysteresis
UTD–10°C10°C4.5 sHysteresis